Silicon-on-insulator (SOI) technology provides an optimal structure for realizing monolithic radiation imaging devices as it involves the preparation of a separate thick silicon layer for the sensing region in addition to a circuit layer. However, several difficult issues exist in the use of commercial SOI-CMOS processes to fabricate the imaging devices. We have developed an SOI pixel process based on an 0.2 µm fully-depleted (FD)-SOI CMOS process. To achieve a thick sensing region, we have bonded a high-resistivity floating-zone (FZ) wafer as the handle wafer. Since the device must be radiation-hardened, a new double SOI process technology is developed to improve the radiation hardness to more than 100 kGy(Si) and reduce the coupling between sensors and circuits. The SOI pixel process and sensors we developed are shown.