An Overlay Architecture for Pattern Matching

Abstract

It is the dream of a young woman from a destroyed third-world country in the Middle East, suffered fear, faith persecution, and insecurity. Seven years in first-world country where everything is new, starting from nowhere and stepping through many challenges. With two little sons and husband, living the happiness, unhappiness, success, disappointments, longing to reunite with the parents, and the fear of the unknown future. Proudly, I'm presenting my dissertation, the outcome of this journey, and it would not have been possible without the contribution of several people. First, I would like to express my sincere gratitude to my advisor Dr. Jason Bakos, for his exemplary support, patience and guidance throughout my doctoral studies.

New Regular Expressions on Old Accelerators

“…Existing work addressing pattern update times focuses either on better utilizing FPGA toolchains [9] which still leaves pattern update times orders of magnitude too long, or on introducing architectures that make reconfigurability easier [10], [11]. Of these architectures, generalized FPGA overlays such as NAPOLY [11] reduce compile time drastically, but have far less throughput and capacity than single-level reconfigurable designs [4]. There have been attempts at fast reprogrammability [10] but they lack compiler support, and only support regex replacement rather than regex addition.…”