An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

Takayanagi, Isao; Yoshimura, Norio; Mori, K.; Matsuo, Shin’ichiro; Tanaka, S.; Abe, Hirofumi; Yasuda, Naoto; Ishikawa, Kazuhiko; Okura, Shunsuke; Ohsawa, Shinji; Otaka, Toshinori

doi:10.3390/s18010203

Cited by 20 publications

(12 citation statements)

References 10 publications

(10 reference statements)

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“…Notably, the high EQE covering the near-infrared region is better than most commercial silicon-based imaging sensors, which are potential applications in mobile-phone-based facial recognition and surveillance cameras . Regarding dynamic range behavior, Sn-rich binary PVSK–PDs achieve an dynamic range of 100 dB (see Figure S11), which is better than that of commercial imaging sensors (∼60 dB) and is comparable to state-of-the-art wide-dynamic-range imaging sensors (∼100 dB). − …”

Section: Resultsmentioning

confidence: 95%

Achieving High-Quality Sn–Pb Perovskite Films on Complementary Metal-Oxide-Semiconductor-Compatible Metal/Silicon Substrates for Efficient Imaging Array

et al. 2019

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Although Sn−Pb perovskites sensing nearultraviolet−visible−near-infrared light could be an attractive alternative to silicon in photodiodes and imaging, there have been no clear studies on such devices constructed on metal/ silicon substrates, hindering their direct integration with complementary metal-oxide semiconductor (CMOS) and silicon electronics. Typically, high surface roughness and severe pinholes of Sn-rich binary perovskites make it difficult for them to fulfill the requirements of efficient photodiodes and imaging. These issues cause inherently high dark current and poor (dark and photo-) current uniformity. Herein, we propose and demonstrate the room-temperature crystallization in the Sn-rich binary perovskite system to effectively control film crystallization kinetics. With experimental and theoretical studies of the crystallization mechanism, we successfully tune the density and location of nanocrystals in precursor films to achieve compact nanocrystals, which coalesce into high-quality (smooth, dense, and pinhole-free) perovskites with intensified preferred orientation and decreased trap density. The high-quality perovskites reduce dark current and improve (dark and photo-) current uniformity of perovskite photodiodes on CMOS-compatible metal/silicon substrates. Meanwhile, self-powered devices achieve a high responsivity of 0.2 A/W at 940 nm, a large dynamic range of 100 dB, and a fast fall time of 2.27 μs, exceeding those of most silicon-based imaging sensors. Finally, a 6 × 6 pixel integrated photodiode array is successfully demonstrated to realize the imaging application. The work contributes to understanding the fundamentals of the crystallization of Sn-rich binary perovskites and advancing perovskite integration with Si-based electronics.

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Section: Resultsmentioning

confidence: 95%

Achieving High-Quality Sn–Pb Perovskite Films on Complementary Metal-Oxide-Semiconductor-Compatible Metal/Silicon Substrates for Efficient Imaging Array

et al. 2019

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“…The authors reported an over 87 dB SEHDR CIS with a 3.0 µm pixel introducing a high full-well capacity (FWC) photodiode (PD) and a multiple gain pixel technology [1][2][3][4]. In the previous sensor, photoelectrons accumulated in the photodiode are read out two times in different gains, then combined into an HDR signal.…”

Section: Introductionmentioning

confidence: 99%

A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor

Takayanagi¹,

Miyauchi²,

Okura

et al. 2019

Sensors

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In this paper, a prototype complementary metal-oxide-semiconductor (CMOS) image sensor with a 2.8-μm backside-illuminated (BSI) pixel with a lateral overflow integration capacitor (LOFIC) architecture is presented. The pixel was capable of a high conversion gain readout with 160 μV/e− for low light signals while a large full-well capacity of 120 ke− was obtained for high light signals. The combination of LOFIC and the BSI technology allowed for high optical performance without degradation caused by extra devices for the LOFIC structure. The sensor realized a 70% peak quantum efficiency with a normal (no anti-reflection coating) cover glass and a 91% angular response at ±20° incident light. This 2.8-μm pixel is potentially capable of higher than 100 dB dynamic range imaging in a pure single exposure operation.

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“…Even with the 100 dB difference in the illumination levels, all the color objects are clearly captured without saturation. A. Tournier et.al [3] T. Yokoyama et.al [5] M. Kobayashi et.al [6] L. Stark et.al [9] T. Kondo et.al [8] I. Takayanagi et.al [13,14] Process…”

Section: Fabrication and Characterization Resultsmentioning

confidence: 99%

“…The charge storage region and the other driving circuits are located in the bottom layer. This SEHDR GS pixel was designed with three key technologies: (i) a multiple gain readout structure with additional BIN [12,13] and in-pixel capacitor; (ii) a high charge density PD [14]; (iii) the two sets of S/H capacitors for CDS operation in both high conversion gain (HCG) mode and low conversion gain (LCG) mode. The stacked pixel configuration with the two sets of different conversion gain signal storage realizes the GS operation with SE and ME HDR functions [9,13,14].…”

Section: New Stacked Bsi Voltage Domain Global Shutter Cmos Image Senmentioning

confidence: 99%

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Miyauchi¹,

Mori²,

Otaka³

et al. 2020

Sensors

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A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

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An Over 90 dB Intra-Scene Single-Exposure Dynamic Range CMOS Image Sensor Using a 3.0 μm Triple-Gain Pixel Fabricated in a Standard BSI Process

Cited by 20 publications

References 10 publications

Achieving High-Quality Sn–Pb Perovskite Films on Complementary Metal-Oxide-Semiconductor-Compatible Metal/Silicon Substrates for Efficient Imaging Array

Achieving High-Quality Sn–Pb Perovskite Films on Complementary Metal-Oxide-Semiconductor-Compatible Metal/Silicon Substrates for Efficient Imaging Array

A 120-ke− Full-Well Capacity 160-µV/e− Conversion Gain 2.8-µm Backside-Illuminated Pixel with a Lateral Overflow Integration Capacitor

A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

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