2021
DOI: 10.32604/cmc.2021.017575
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An Optimized SW/HW AVMF Design Based on High-Level Synthesis Flow for Color Images

Abstract: In this paper, a software/hardware High-level Synthesis (HLS) design is proposed to compute the Adaptive Vector Median Filter (AVMF) in realtime. In fact, this filter is known by its excellent impulsive noise suppression and chromaticity conservation. The software (SW) study of this filter demonstrates that its implementation is too complex. The purpose of this work is to study the impact of using an HLS tool to design ideal floating-point and optimized fixed-point hardware (HW) architectures for the AVMF filt… Show more

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Cited by 4 publications
(2 citation statements)
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“…Complex systems can only be developed by hardware designers with specific knowledge and abilities. In order to simplify the complexity of the FPGA design, Low-Level Synthesis must be replaced by High-Level Synthesis (HLS) [55][56][57]. Using software high-level languages (systemC, C/C + +, etc.…”
Section: Introductionmentioning
confidence: 99%
“…Complex systems can only be developed by hardware designers with specific knowledge and abilities. In order to simplify the complexity of the FPGA design, Low-Level Synthesis must be replaced by High-Level Synthesis (HLS) [55][56][57]. Using software high-level languages (systemC, C/C + +, etc.…”
Section: Introductionmentioning
confidence: 99%
“…Nevertheless, only hardware designers with specialized knowledge and abilities are capable of creating a sophisticated system. Therefore, in order to decrease the complexity of the FPGA design, it is imperative to go from Low-Level Synthesis (LLS) to High-Level Synthesis (HLS) [ 53 , 54 , 55 ]. The HLS tool synthesizes the formalized algorithms into a behavioral and structural RTL hardware description utilizing software high-level languages (systemC, C/C++, etc.).…”
Section: Introductionmentioning
confidence: 99%