An Optimized Start-up Scheme for Isolated Cascaded AC/DC Power Converters

Jean-Pierre, Garry; Tripathi, Awneesh; Burugula, Vasistha; Bhavaraju, Vijay

doi:10.1109/ecce50734.2022.9947713

Cited by 3 publications

(1 citation statement)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…1(a) [2]. The operation of the MV SST PCS at 24kV DC requires a soft start-up scheme to build up DC link voltage without high inrush currents [3]- [4]. Sachin et al have demonstrated the regulation of DC link voltage and grid current during soft start-up operation for cascaded Medium Voltage (MV) AFEC and DAB [5].…”

Section: Introductionmentioning

confidence: 99%

Overvoltage Protection of Series-Connected 10kV SiC MOSFETs Following Switch Failures in MV 3L-NPC Converter for Safe Fault Isolation and Shutdown

Parashar,

Isik,

Kolli

et al. 2024

IEEE Access

View full text Add to dashboard Cite

This paper presents a design methodology for overvoltage protection across 10kV SiC MOSFETs during turn-off after switch failure in a MV SST Power Conditioning System (PCS) enabled by a cascaded Three-Phase (3P) Three-level (3L) Neutral Point Clamped (NPC) Active Front-End Converter (AFEC) and Dual Active Bridge (DAB) using series-connected 10kV SiC MOSFETs and 10kV SiC JBS diodes. The methodology uses an active voltage clamp at the gate terminal and desat detection technique to identify abrupt open and turn-on switch failures across series-connected 10kV SiC MOSFETs. The analytical model estimates over-current time and turn-off voltage transition by considering bus bar inductance, device base plate capacitance and common mode (CM) choke tied between the heat sink and midpoint of the DC link capacitor. The transition model is used to evaluate the turn-off timing for series-connected MOSFETs, snubber resistors, snubber capacitors, and gate resistors to avoid MOSFET overvoltage during converter shutdown, without affecting the voltage balancing and efficiency during normal operation. The MOSFET turn-off transition during the shutdown has been verified in the Saber RD simulation using the validated Saber RD MAST model of 10kV SiC MOSFETs and 10kV SiC JBS diodes at 13.8kV AC/24kV DC level. The fault isolation and MV SST PCS shutdown have been verified in a real-time environment using HIL setup with Xilinx FPGAs and RTDS, at 13.8kV AC/24kV DC link under PCS operating conditions. The normal operation of 3L-NPC pole hardware with modified snubber resistors, snubber capacitors, and gate resistors is verified by experiments conducted at 7kV DC, 10A load current.

show abstract