An Optimized Packet Transceiver Design for Ethernet-MAC Layer Based on FPGA

Guruprasad, S. P.; Chandrasekar, B. S.

doi:10.1007/978-3-030-03146-6_82

Cited by 2 publications

(1 citation statement)

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“…The Hardware architecture of the Ethernet MAC transceiver architecture [20] is represented in Figure 3, which is having Receiver and transmitter models. The receiver model contains receiver-Finite state machine (FSM), Frame Length Counter (FLC), CRC, Receiver-FIFO.…”

Section: Bridge Modelmentioning

confidence: 99%

Performance realization of Bridge Model using Ethernet-MAC for NoC based system with FPGA Prototyping

Guruprasad

Chandrasekar

2020

IJEEI

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The System on Chip (SoC) integrates the number of processing elements (PE) with different application requirements on a single chip. The SoC uses busbased interconnection with shared memory access. However, buses are not scalable and limited to particular interface protocol. To overcome these problems, The Network on Chip (NoC) is an emerging interconnect solution with a scalable and reliable solution over SoC. The bridge model is essential to communicate the NoC based system on SoC. In this article, a cost-effective and efficient bridge model with ethernet-MAC is designed, and also the placement of the bride with NoC based system is prototyped on Artix-7 FPGA. The Bridge model mainly contains FIFO modules, Serializer and deserializer, a priority-based arbiter with credit counter, packet framer, and packet parser with Ethernet-MAC transceiver Module. The Bridge with a single router and different sizes of the NoC based systems with mesh topology are designed using adaptive-XY routing. The performance metrics are evaluated for Bridge with NoC in terms of average Latency and maximum throughput for different Packet Injection Rate (PIR).

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Section: Bridge Modelmentioning

confidence: 99%