An Optimization Methodology for Designing Hardware-Based Function Evaluation Modules with Reduced Complexity

González-Díaz_Conti, Griselda; Longoria-Gándara, O.; Carrasco-Alvarez, Roberto; Ruiz-Ibarra, Erica; Atoche, A. Castillo; Castillo, J. Vázquez

doi:10.1007/s00034-021-01835-1

Cited by 1 publication

(4 citation statements)

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“…This study employs the PPA technique with a wordlength-efficient decoder (PPA-ED) methodology described in [35] to design the proposed AFC for HNN implementations. A comparative analysis is also provided to show the advantages of the proposed methodology with the minimax approximation [29], the simple canonical piecewise linear (SCPWL) [32], and the piecewise linear approximation computation (PLAC) [15].…”

Section: Ppa Implementation Methodologiesmentioning

confidence: 99%

“…The PPA-ED [35] optimizes the polynomial indexation and improves previous methodologies [15,29,32] for the hardware design of AFs according to the MAE, MSE, AAE, and SQNR metrics. This study customizes the PPA-ED to design AFCs in HNN implementations on FPGAs.…”

Section: Ppa With Wordlength-efficient Decodermentioning

confidence: 99%

“…The adaptive segmentation, the polynomial approximation, the quantization, and the optimization processes of PPA-ED reduce hardware resources used in the design. The used methodology automatically sets up the PPA segment limits, computed as linear combinations of power-of-two, using a detection algorithm based on the function slope and the user-defined parameters in order to achieve the desired performance and optimize the polynomial indexation [35]. Likewise, PPA-ED computes the n + 1 coefficients of n-degree for the K segments applying the Vandermonde Matrix [37].…”

Section: Ppa With Wordlength-efficient Decodermentioning

confidence: 99%

“…The AFC implementation employs a design framework based on the proposed methodology [35]. Figure 2 shows the design framework for implementing the AFC in HNN.…”

Section: Afc Hardware Implementationmentioning

confidence: 99%

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Hardware-Based Activation Function-Core for Neural Network Implementations

et al. 2021

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Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

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Section: Ppa Implementation Methodologiesmentioning

confidence: 99%

Section: Ppa With Wordlength-efficient Decodermentioning

confidence: 99%

Section: Ppa With Wordlength-efficient Decodermentioning

confidence: 99%

“…The AFC implementation employs a design framework based on the proposed methodology [35]. Figure 2 shows the design framework for implementing the AFC in HNN.…”

Section: Afc Hardware Implementationmentioning

confidence: 99%

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