An Optimal Algorithm for Designing NCO Circuit in Mobile Communication Systems

Hu, Shuhua; Li, Hui; Huang, Junfei

doi:10.1109/cmc.2009.132

Cited by 4 publications

(1 citation statement)

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“…In [5], DDC generates a signal pulse to sample an RRC filter. In [6,7,8], DDC uses CORDIC IP cores to generate sine and cosine signals when mixing the FPGA. My optimization method is to extract the number of points of the local oscillator signal required for mixing in one cycle through MATLAB, and write it directly to the FPGA for implementation, which has the advantage of saving the logic computing resources of the hardware.…”

Section: Introductionmentioning

confidence: 99%

An error verification design of DDC based on MATLAB and FPGA

Deng,

Tang

2023

Third International Conference on Advanced Algorithms and Signal Image Processing (AASIP 2023)

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The main work of this paper is to study the error verification problem of radar echo signal DDC algorithm implementation, and DDC has certain innovations in hardware implementation methods. The main design modules of DDC include band-pass filtering, mixing, low-pass filtering, decimation and zeroing. In the design and verification of DDC system, the time-domain dual-frequency chirp echo signal is first simulated, and the DDC processing process is verified by advanced floating-point simulation on the MATLAB platform to verify its feasibility and correctness. Then, through Verilog HDL programming, the FPGA-based DDC implementation is carried out, and the output results of each module are simulated through Medelsim. Finally, the simulation results in each FPGA module are calculated with the simulation results in MATLAB to verify the accuracy of the hardware design.

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