The solution mixing method was adopted to build polymer semiconductor poly(9,9-dioctylflfluorene-co-benzothiadiazole) (F8BT) nanoparticles (NPs), which were mixed with poly (methyl methacrylate) (PMMA) in a solution to prepare an integrated floating-gate/tunneling layer. On this basis, flexible floating-gate based organic field-effect transistor non-volatile memories (F-OFET-NVMs) were prepared. The intrinsic correlations of the microstructures in the integrated floating-gate/tunneling layer of the memory devices with the device performance were explored. Moreover, correlations of the charge injection and discharge, physical mechanism of memory, and charge trapping capacity of the floating-gate/tunneling layer with different F8BT/PMMA mass ratios with the key parameters of memory devices were investigated. Relevant results indicate that the memory devices are able to well trap charges inside the F8BT NPs during operation at a programming voltage of +40 V, an erasing voltage of -40 V, and a pulse width of 1 s. The floating gate acquires the injected and trapped bipolar charges (electrons and holes). The optimized high-performance memory device is found to have an average memory window of 9.5 V, remain stable for more than three years, and have reliable stability in more than 100 erase/write cycles. Furthermore, the memory device also exhibits outstanding durability under mechanical bending and still has high storage stability after 6,000 times of bending with a bending radius of 3 mm. The research results powerfully promote the research progress of applying semiconductor polymers to memory devices.