An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture

Abstract

With the emergence of Non-Volatile Memories (NVMs) and their shortcomings such as limited endurance and high power consumption in write requests, several studies have suggested hybrid memory architecture employing both Dynamic Random Access Memory (DRAM) and NVM in a memory system. By conducting a comprehensive experiments, we have observed that such studies lack to consider very important aspects of hybrid memories including the effect of: a) data migrations on performance, b) data migrations on power, and c) the granularity of data migration. This paper presents an efficient data migration scheme at the Operating System level in a hybrid DRAM-NVM memory architecture. In the proposed scheme, two Least Recently Used (LRU) queues, one for DRAM section and one for NVM section, are used for the sake of data migration. With careful characterization of the workloads obtained from PARSEC benchmark suite, the proposed scheme prevents unnecessary migrations and only allows migrations which benefits the system in terms of power and performance. The experimental results show that the proposed scheme can reduce the power consumption up to 79% compared to DRAM-only memory and up to 48% compared to the state-of-the art techniques.

An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories

“…CLOCK-DWF [17] uses two CLOCK data structures to manage DRAM and NVM memory modules and decide page demotions from DRAM to NVM. To reduce the migration cost in terms of performance and endurance, UH-MEM [12] and TwoLRU [18] aim to limit the migrations by estimating their benefit and cost.…”

“…In order to take advantage of the promising characteristics of NVMs while minimizing the effect of their limitations, previous studies suggested employing Hybrid Memory Architectures (HMAs) composed of DRAM and NVMs in a single level or multiple levels of the memory hierarchy [8], [10], [11], [12], [13], [14], [15], [16], [17], [18], [19], [20], [21], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34]. Fig.…”

A Task Scheduling Scheme Considering Hybrid Main Memory and Interactive Tasks

“…As a result, shown in Figure 1, hybrid main memory using DRAM and NVRAM seems to be practicable instead of pure NVRAM-based main memory in the near future. Some recent studies have introduced NVRAM-based main memory organization [13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29]. However, legacy bandwidth-aware multi-core scheduling methods can not applicable with the DRAM/NVRAM hybrid main memory.…”

“…As a result, hybrid main memory using DRAM and NVRAM seems to be practicable instead of pure NVRAM-based main memory in the near future. Some recent studies have introduced NVRAM-based hybrid main memory organization [20][21][22][23][24][25][26][27][28][29].…”

Fine-Grained Data Management for DRAM/SSD Hybrid Main Memory Architecture

“…Fortunately, the advent of Non-Volatile Memory (NVM) technologies offers a promising opportunity for memory organization. Some projects propose to construct hybrid main memory using NVM devices such as PCM and STT-RAM [1], [2]. Nevertheless, the above researches are usually proceeded using architecture simulators and empirical models because mature products based on these memory technologies are not yet available.…”