An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers

Abdulgadir, Abubakr; Diehl, William; Kaps, Jens-Peter

doi:10.1109/reconfig48160.2019.8994788

Cited by 11 publications

(8 citation statements)

References 7 publications

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“…The setup is built specially for measuring FPGA core power for physical side-channel attack analysis. The setup is termed as FOBOS (Flexible Open-source workBench fOr Side-channel analysis) [56,57]. Figure 12 shows the block diagram of the FOBOS setup, Figure 13 is a photo of the components connected together for power measurement.…”

Section: Fobos Setupmentioning

confidence: 99%

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Reverse Engineering of Integrated Circuits: Tools and Techniques

Dhavlle¹

2022

Preprint

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Consumer and defense systems demanded design and manufacturing of electronics with increased performance, compared to their predecessors. As such systems became ubiquitous in a plethora of domains, their application surface increased, thus making them a target for adversaries. Hence, with improved performance the aspect of security demanded even more attention of the designers. The research community is rife with extensive details of attacks that target the confidential design details by exploiting vulnerabilities. The adversary could target the physical design of a semiconductor chip or break a cryptographic algorithm by extracting the secret keys, using attacks that will be discussed in this thesis. This thesis focuses on presenting a brief overview of IC reverse engineering attack and attacks targeting cryptographic systems. Further, the thesis presents my contributions to the defenses for the discussed attacks. The globalization of the Integrated Circuit (IC) supply chain has rendered the advantage of low-cost and high performance ICs in the market for the end users. But this has also made the design vulnerable to over production, IP Piracy, reverse engineering attacks and hardware malware during the manufacturing and post manufacturing process. Logic locking schemes have been proposed in the past to overcome the design trust issues but the new state-of-the-art attacks such as SAT has proven a larger threat. This work highlights the reverse engineering attack and a proposed hardened platform along with its framework. On the other side, the side-channel attacks (SCAs) has been one of the emerging threats. These SCAs function by exploiting the side-channels which invariably leak important data during an application's execution. The information leaked through side-channels are inherent characteristics of the system and is often unintentional. This information can be microarchitectural or physical information such as power consumption, thermal maps, timing of the operation, acoustics, and cache-trace. Intercepting secret information based on the study of power signature is a subdivision of SCAs where power consumption information serves as a covert channel leaking crucial information about the executed operations. Such physical SCAs are known to be a significant threat to cryptosystems such as AES (Advanced Encryption Standard) and can reveal the encryption key efficiently. To overcome such concerns and protect the data integrity, I introduce Power Swapper in this work. The proposed Power Swapper thwarts the attack by randomly choosing one of the multiple modules that perform the intended activity, but have power signature different than a standard implementation and can lead to similar power consumption as one of the other modules that perform a different operation. To achieve this, I introduce carefully crafted swapping of the standby modules that are responsible for the AES operation thus deluding the attacker without hurting the crypto operation. This methodology has been validated for the AES power analysis ...

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Section: Fobos Setupmentioning

confidence: 99%

“…The FOBOS is completely reconfigurable to suit the specific needs of the measurements and application. The setup is described in more detail in [56,57].…”

Section: Fobos Setupmentioning

confidence: 99%

Reverse Engineering of Integrated Circuits: Tools and Techniques

Dhavlle¹

2022

Preprint

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“…Abdulgadir et al [238] developed FOBOS2 -an improved version of FOBOS (Flexible Opensource workBench fOr Side-channel analysis) -to perform power measurements and side-channel resistance evaluations of the candidates. Results on SpoC, Spook, GIFT-COFB, ASCON, and AES-GCM are measured.…”

Section: Side-channel Resistancementioning

confidence: 99%

Status report on the second round of the NIST lightweight cryptography standardization process

Turan¹,

McKay²,

Chang³

et al. 2021

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The National Institute of Standards and Technology (NIST) initiated a public standardization process to select one or more Authenticated Encryption with Associated Data (AEAD) and hashing schemes suitable for constrained environments. In February 2019, 57 candidates were submitted to NIST for consideration. Among these, 56 were accepted as firstround candidates in April 2019. After four months, NIST selected 32 of the candidates for the second round. In March 2021, NIST announced 10 finalists to move forward to the final round of the selection process. The finalists are ASCON, Elephant, GIFT-COFB, Grain-128AEAD, ISAP, PHOTON-Beetle, Romulus, SPARKLE, TinyJAMBU, and Xoodyak. This report describes the evaluation criteria and selection process, which is based on public feedback and internal review of the second-round candidates.

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“…← (( + ) (0) ) || ( + ) (1) 7: end for Further decreasing the number of clock cycles would require doubling the number of BRAMs, which would make them highly underutilized. Instead, matrices and , as well as constants , could be stored in distributed memory located in LUTs.…”

Section: Algorithm 2 Unrolled Lowmc Pseudocodementioning

confidence: 99%

“…The Flexible Open-source workBench fOr Side-channel analysis (FOBOS) is an SCA platform suitable for data acquisition and analysis [1,25,26]. This platform consists of a data acquisition module used to collect power traces and an analysis module used to mount side-channel attacks and perform leakage assessment.…”

Section: Fobos Platformmentioning

confidence: 99%

Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks

Bahrami

Dang

Abdulgadir

et al. 2020

Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security

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LowMC is a parameterizable block cipher developed for use in Multi-Party Computation (MPC) and Fully Homomorphic Encryption (FHE). In these applications, linear operations are much less expensive in terms of resource utilization compared to the nonlinear operations due to their low multiplicative complexity. In this work, we implemented two versions of LowMC-unrolled and lightweight. Both implementations are realized using RTL VHDL. To the best of our knowledge, we report the first lightweight implementation of LowMC and the first implementation protected against side-channel analysis (SCA). For the SCA protection, we used a hybrid 2/3 shares Threshold Implementation (TI) approach, and for the evaluation, the Test Vector Leakage Assessment (TVLA) method, also known as the T-test. Our unprotected implementations show information leakage at 10K traces, and after protection, they could successfully pass the T-test for 1 million traces. The Xilinx Vivado is used for the synthesis, implementation, functional verification, timing analysis, and programming of the FPGA. The target FPGA family is Artix-7, selected due to its widespread use in multiple applications. Based on our results, the numbers of LUTs are 867 and 3,328 for the lightweight and the unrolled architecture with unrolling factor = 16, respectively. It takes 14.21 s for the lightweight architecture and 1.29 s for the unrolled design with = 16 to generate one 128-bit block of the ciphertext. The fully unrolled architecture beats the best previous implementation by Kales et al. in terms of the number of LUTs by a factor of 4.5. However, this advantage comes at the cost of having 2.9 higher latency.

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An Open-Source Platform for Evaluation of Hardware Implementations of Lightweight Authenticated Ciphers

Cited by 11 publications

References 7 publications

Reverse Engineering of Integrated Circuits: Tools and Techniques

Reverse Engineering of Integrated Circuits: Tools and Techniques

Status report on the second round of the NIST lightweight cryptography standardization process

Lightweight Implementation of the LowMC Block Cipher Protected Against Side-Channel Attacks

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