An Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processors

Liao, Chien-Hui; Wen, Charles H.-P.; Chakrabarty, Krishnendu

doi:10.7873/date.2015.0724

Cited by 20 publications

(6 citation statements)

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“…In [27], thermal‐pattern‐aware VA (TPAVA) was proposed as a method to reduce thermal hotspots by assigning different initial voltage levels to the cores. Our experimental results show that the throughput improvement provided by TPAVA is limited because it does not adjust the VA at runtime.…”

Section: Resultsmentioning

confidence: 99%

“…As a result, the proposed TADVA2.0 strategy significantly improves on the previous work by simultaneously reducing hotspots, optimising throughput and minimising energy consumption for 3D-MCPs with thermal constraints. Table 6 Compared to the baseline STSC + C_DVFS task scheduler, the performance of the STSC + P_DVFS [7], STSC + C_DVFS + TPAVA [27] and STSC + C_DVFS + TADVA2.0 task schedulers Task schedulers HRR, % TIR, % ESP, %…”

Section: Discussionmentioning

confidence: 99%

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Online task scheduler in 3D‐MCPs with TADVA

Liao

Wen²

2018

IET Computers & Digital Techniques

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Hotspots occur frequently in three-dimensional (3D) multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. The authors present dynamic-voltage-assignment (DVA) strategies that reduce hotspots in and optimise the performance of 3D-MCPs by pre-emptively selecting voltages among low-power and highperformance operating modes. The proposed DVA strategies can be employed in online, thermally constrained task schedulers. Three DVA strategies, random DVA, thermal-aware DVA (TADVA) and TADVA2.0, are proposed to reduce the temperature increase in 3D-MCPs by pre-emptively and dynamically estimating the optimum VAs for all cores in the processor during runtime once the chip begins operating. In particular, TADVA2.0 uses the temperature-variation rates of the cores and takes into account two important thermal behaviours of 3D-MCPs that can effectively limit the temperature increase in 3D-MCPs. Experimental results indicate that, when compared with two previous online thermally constrained task schedulers, the proposed task scheduler with their novel DVA strategy can reduce hotspot occurrences by ∼60% and improve throughput by ∼8%. These results indicate that the proposed TADVA2.0 strategy is an effective technique for suppressing hotspot occurrences and optimising throughput for 3D-MCPs subject to thermal constraints.

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Section: Resultsmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Online task scheduler in 3D‐MCPs with TADVA

Liao

Wen²

2018

IET Computers & Digital Techniques

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“…This proposed technique can improve performance by 7.2% over the base processor. In [2], a new thermal-constrained task scheduler based on Thermal-Pattern-Aware…”

Section: Task Schedulingmentioning

confidence: 99%

Run-time thermal management based on task migration techniques in 3D chip multiprocessors

Aljeddani¹

2021

Preprint

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The industry trend of Chip Multiprocessors (CMPs) architecture is to move from 2D CMPs to 3D CMPs architecture for obtain higher performance, more reliability, and reduced memory access latency. However, one key challenge in designing the 3D CMPs is the thermal issue as a result of maximizing the throughput . Therefore, applying Runtime Thermal Management (RTM) has become crucial for controlling thermal hotspots. In this thesis, two methods of run-time task migration are presented to balance the temperature and reduce the number of hotspots in 3D CMPs. The proposed techniques consider hotspots both in the core and the memory layers simultaneously to make the optimum run-time task migration decisions. The first proposed approach is divided into two algorithms working in parallel, which aim at maximizing the throughput on the 3D CMPs while satisfying the peak temperature constraints. Experimental results show that the proposed architecture yields up to 60% reduction in overall chip energy. The proposed architecture improves the IPC for canneal and fluidanimate applications by 18% and 14%, respectively. In the second method, the proposed technique migrates the hottest core with the optimal coldest core instead of the coldest core in the core layer. The optimal coldest core is selected by considering hotspots.

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“…A new thermal constrained task scheduling method based on thermal-pattern-aware voltage assignment (TPAVA) has been proposed in [29]. By analysing the temperature profiles of different voltage assignments, TPAVA preemptively assigns different operating voltage levels to cores to reduce the temperature.…”

Section: Related Workmentioning

confidence: 99%

Temperature‐aware core management in MPSoCs: modelling and evaluation using MRMs

Taheri¹,

Khonsari²,

Entezari‐Maleki³

et al. 2019

IET Computers & Digital Techniques

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With successive scaling of CMOS technology, power density and cooling costs significantly increase. Consequently, the cooling system of processors can no longer be designed for the worst-case situation in each generation of CMOS technology and there is an essential need for run-time techniques to control the operating temperature. Task scheduling and resource management with respect to thermal constraints are run-time methods used to control the thermal profile of a system. In this study, the authors use Markov Reward Models (MRMs) to model and evaluate a new core thermal management method, which can reduce hotspots and balance the thermal profile of a multi-core system. Although the proposed management method degrades the performance of the system, such as other previously presented methods, it controls the temperature of a die to decrease the temperature variation and hotspots. The proposed approach is assessed on a quad-core system and the experimental results are compared to the results obtained from the proposed MRM to demonstrate the accuracy of the proposed analytical model.

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An Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processors

Cited by 20 publications

References 0 publications

Online task scheduler in 3D‐MCPs with TADVA

Online task scheduler in 3D‐MCPs with TADVA

Run-time thermal management based on task migration techniques in 3D chip multiprocessors

Temperature‐aware core management in MPSoCs: modelling and evaluation using MRMs

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