An on-line test strategy and analysis for a 1T1R crossbar memory

Escudero-Lopez, Manuel; Moll, Francesc; Rubio, Antonio; Vourkas, Ioannis

doi:10.1109/iolts.2017.8046206

Cited by 4 publications

(4 citation statements)

References 10 publications

(11 reference statements)

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“…Despite the fact that memristor-based crossbar array designs have already been presented [53], [54], [55], mixed circuits with individual memristor and transistor devices for ASICs need ad hoc design. Since MemCA transistor-level design does not constitute a trivial task, in this section, the transistor-level design of the proposed MemCA hardware realization is presented.…”

Section: Memca Circuit Designmentioning

confidence: 99%

MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization

et al. 2023

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Inspired by the behavior of natural systems, Cellular Automata (CA) tackle the demanding long-distance information transfer of conventional computers by the massive parallel computation performed by a set of locally-coupled dynamical nodes. Although CA are envisioned as powerful deterministic computers, their intrinsic capabilities are expanded after the memristor's probabilistic switching is introduced into CA cells, resulting in new hybrid deterministic and probabilistic memristor-based CA (MemCA). In the proposed MemCA hardware realization, memristor devices are incorporated in both the cell and rule modules, composing the very first all-memristor CA hardware, designed with mixed CMOS/Memristor circuits. The proposed implementation accomplishes high operating speed and reduced area requirements, exploiting also memristor as an entropy source in every CA cell. MemCA's functioning is showcased in deterministic and probabilistic operation, which can be externally modified by the selection of programming voltage amplitude, without changing the design. Also, the proposed MemCA system includes a reconfigurable rule module implementation that allows for spatial and temporal rule inhomogeneity.

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Section: Memca Circuit Designmentioning

confidence: 99%

MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization

et al. 2023

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“…In addition, as the fabrication technology improves and the device dimensions shrink, the line resistance in CPAs is becoming a serious issue [5,6]. CPAs are not exempt from suffering faults related to the switching capability both associated with the fabrication process and with the lifetime of the devices [7][8][9][10]. This work explores the possibility of investigating reliability aspects of CPAs from a system-level approach.…”

Section: Introductionmentioning

confidence: 99%

Simple method for monitoring the switching activity in memristive cross-point arrays with line resistance effects

Miranda

Morell

Muñoz-Gorriz

et al. 2019

Microelectronics Reliability

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A simple method for monitoring the switching activity (forming, set, reset events and stuck-at-0/1 faults) in memristive cross-point arrays with line resistance effects is proposed. The method consists in correlating incremental current changes in a four-terminal configuration with the location of the switching cell within the array. To this end the potential drop in the interconnection wires as well as the nonlinearity of the switching elements are considered. The problem is solved by iterating the Kirchhoff's current law for the coupled word and bit lines with appropriate boundary conditions. The main experimental advantage of the proposed method is that only four SMUs (source-measurement unit) are needed to identify the switching cell. In this way, our method could greatly contribute to foster the system-level reliability analysis of cross-point arrays since additional circuitry for the individual addressing of the switching device is not required.

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“…This Chapter presents a review of the possibilities that memristors offer as part of memory systems. Next, a novel strategy to test faulty cells in memristor-based memory arrays is presented (published in [72]). Such strategy spans the whole space from the design of the memory circuit to the algorithm that detects different kinds of known faults for this type of devices.…”

Section: Chapter 4 Fault Testing In Memristor-based Memory Systemsmentioning

confidence: 99%

“…This Section presents a procedure to test a one-transistor-one-memristor (1T1R) crossbar-based memristive memory array during normal operation of the system, published in [72]. Such procedure focuses specifically on the different malfunctions of the memory cells.…”

Section: Online Testing Strategy For Faults In 1t1r Crossbar Memorymentioning

confidence: 99%

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

Escudero López

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In the last decades, semiconductor industry has fostered a fast downscale in technology, propelling the large scale integration of CMOS-based systems. The benefits in miniaturization are numerous, highlighting faster switching frequency, lower voltage supply and higher device density. However, this aggressive scaling trend it has not been without challenges, such as leakage currents, yield reduction or the increase in the overall system power dissipation. New materials, changes in the device structures and new architectures are key to keep the miniaturization trend. It is foreseen that 2D integration will eventually come to an insurmountable physical and economic limit, in which new strategic directions are required, such as the development of new device structures, 3D architectures or heterogeneous systems that takes advantage of the best of different technologies, both the ones already consolidated as well as emergent ones that provide performance and efficiency improvements in applications. In this context, memristor arises as one of several candidates in the race to find suitable emergent devices. Memristor, a blend of the words memory and resistor, is a passive device postulated by Leon Chua in 1971. In contrast with the other fundamental passive elements, memristors have the distinctive feature of modifying their resistance according to the charge that passes through these devices, and remaining unaltered when charge no longer flows. Although when it appeared no physical device implementation was acknowledged, HP Labs claimed in 2008 the manufacture of the first real memristor. This milestone triggered an unexpectedly high research activity about memristors, both in searching new materials and structures as well as in potential applications. Nowadays, memristors are not only appreciated in memory systems by their nonvolatile storage properties, but in many other fields, such as digital computing, signal processing circuits, or non-conventional applications like neuromorphic computing or chaotic circuits. In spite of their promising features, memristors show a primarily downside: they show significant device variation and limited lifetime due degradation compared with other alternatives. This Thesis explores the challenges that memristor variation and malfunction imposes in potential applications. The main goal is to propose circuits and strategies that either avoid reliability problems or take advantage of them. Throughout a collection of scenarios in which reliability issues are present, their impact is studied by means of simulations. This thesis is contextualized and their objectives are exposed in Chapter 1. In Chapter 2 the memristor is introduced, at both conceptual and experimental levels, and different compact levels are presented to be later used in simulations. Chapter 3 deepens in the phenomena that causes the lack of reliability in memristors, and models that include these defects in simulations are provided. The rest of the Thesis covers different applications. Therefore, Chapter 4 exhibits nonvolatile memory systems, and specifically an online test method for faulty cells. Digital computing is presented in Chapter 5, where a solution for the yield reduction in logic operations due to memristors variability is proposed. Lastly, Chapter 6 reviews applications in the analog domain, and it focuses in the exploitation of results observed in faulty memristor-based interconnect mediums for chaotic systems synchronization purposes. Finally, the Thesis concludes in Chapter 7 along with perspectives about future work. Este trabajo desarrolla un novedoso dispositivo condensador basado en el uso de la nanotecnología. El dispositivo parte del concepto existente de metal-aislador-metal (MIM), pero en lugar de una capa aislante continua, se utilizan nanopartículas dieléctricas. Las nanopartículas son principalmente de óxido de silicio (sílice) y poliestireno (PS) y los valores de diámetro son 255nm y 295nm respectivamente. Las nanopartículas contribuyen a una alta relación superficie/volumen y están fácilmente disponibles a bajo costo. La tecnología de depósito desarrollada en este trabajo se basa en la técnica de electrospray, que es una tecnología de fabricación ascendente (bottom-up) que permite el procesamiento por lotes y logra un buen compromiso entre una gran superficie y un bajo tiempo de depósito. Con el objetivo de aumentar la superficie de depósito, la configuración de electrospray ha sido ajustada para permitir áreas de depósito de 1cm2 a 25cm2. El dispositivo fabricado, los llamados condensadores de metal aislante de nanopartículas (NP-MIM) ofrecen valores de capacidad más altos que un condensador convencional similar con una capa aislante continua. En el caso de los NP-MIM de sílice, se alcanza un factor de hasta 1000 de mejora de la capacidad, mientras que los NP-MIM de poliestireno exhibe una ganancia de capacidad en el rango de 11. Además, los NP-MIM de sílice muestran comportamientos capacitivos en específicos rangos de frecuencias que depende de la humedad y el grosor de la capa de nanopartículas, mientras que los NP-MIM de poliestireno siempre mantienen su comportamiento capacitivo. Los dispositivos fabricados se han caracterizado mediante medidas de microscopía electrónica de barrido (SEM) complementadas con perforaciones de haz de iones focalizados (FIB) para caracterizar la topografía de los NP-MIMs. Los dispositivos también se han caracterizado por medidas de espectroscopia de impedancia, a diferentes temperaturas y humedades. El origen de la capacitancia aumentada está asociado en parte a la humedad en las interfaces de las nanopartículas. Se ha desarrollado un modelo de un circuito basado en elementos distribuidos para ajustar y predecir el comportamiento eléctrico de los NP-MIMs. En resumen, esta tesis muestra el diseño, fabricación, caracterización y modelización de un nuevo y prometedor condensador nanopartículas metal-aislante-metal que puede abrir el camino al desarrollo de una nueva tecnología de supercondensadores MIM.

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An on-line test strategy and analysis for a 1T1R crossbar memory

Cited by 4 publications

References 10 publications

MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization

MemCA: All-Memristor Design for Deterministic and Probabilistic Cellular Automata Hardware Realization

Simple method for monitoring the switching activity in memristive cross-point arrays with line resistance effects

Reliability-aware circuit design to mitigate impact of device defects and variability in emerging memristor-based applications

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