An on-chip learning neural network

Bo, G.; Caviglia, Daniele D.; Valle, Maurizio

doi:10.1109/ijcnn.2000.860751

Cited by 19 publications

(14 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Learning on chip (LOC) refers to the ability of an embedded system to learn data by it self, then process and classify new unknown data. Some previous works have proposed solutions to train a model on an FPGA, using neural networks [12]. This solutions needs to implement gradient descent which is computationally expensive and quickly becomes a problem when the network size increases.…”

Section: Related Workmentioning

confidence: 99%

Incremental learning on chip

Hacene

Gripon

Farrugia

et al. 2017

2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

View full text Add to dashboard Cite

Learning on chip (LOC) is a challenging problem, which allows an embeded system to learn a model and use it to process and classify unknown data, adapting to new observations or classes. Incremental learning of chip (ILOC) is more challenging. ILOC needs intensive computational power to train the model and adapt it when new data are observed, leading to a very difficult hardware implementation. We adress this issue by introducing a method based on the combination of a pre-trained Convolutional Neural Network (CNN) and majority vote, using Product Quantizing (PQ) as a bridge between them. We detail a hardware implementation of the proposed method validated on an FPGA target, with substantial processing acceleration with few hardware resources.

show abstract

Section: Related Workmentioning

confidence: 99%

Incremental learning on chip

Hacene

Gripon

Farrugia

et al. 2017

2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

View full text Add to dashboard Cite

show abstract

“…Latest neural networks achievements thrive to understand how neuron can be simulated in order to provide better understanding of neuron and more importantly to improve computing and decision making. There is also hardware approach [14] that tries to implement concept of biological neuron on a microscopic level of integrated circuits. By this day, there are electronic chips that can communicate with real and living neurons in brain, this is one direction -human computer interfacing [15]; other is to create computer chips that process information the same way this information is processed in real biological neural networks III.…”

Section: Cognitive and Other Sciencesmentioning

confidence: 99%

Cortex simulation system proposal using distributed computer network environments

Tomas

2014

Preprint

View full text Add to dashboard Cite

show abstract

“…(1), (3), (5) and (9), and in the difference between the T arget and the Out of Eqs. (5) and (6) that is carried out on each output neuron. This mathematical operations will be modified by means of the accomplishment of averages.…”

Section: Microelectronic Limitationsmentioning

confidence: 99%

“…The final aim of this paper has been the design and implementation of a novel neural system in VLSI analogue technology with on-chip by-pattern back propagation learning, [3][4][5][6][7][8][9] as well as to demonstrate its capacity and efficiency in the resolution of classification problems. The main advantages of using an on-chip learning implementation are the small learning times and the compensation of the circuit non-idealities.…”

Section: Introductionmentioning

confidence: 99%

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

et al. 2005

View full text Add to dashboard Cite

In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm 2 . The chip includes two versions of neural nets with onchip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

show abstract

An on-chip learning neural network

Cited by 19 publications

References 17 publications

Incremental learning on chip

Incremental learning on chip

Cortex simulation system proposal using distributed computer network environments

A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

Contact Info

Product

Resources

About