An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Plana, Luis A.; Bainbridge, J.; Furber, Steve; Salisbury, Sean James; Shi, Yebin; Wu, Jian

doi:10.1109/nocs.2008.4492744

Cited by 19 publications

(24 citation statements)

References 2 publications

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“…Its design is based around ad-hoc multi-core System-on-Chips, which are interconnected using a two-dimensional toroidal triangular mesh [10,11]. Neurons are modelled in software and their spikes generate packets that propagate through the on-and inter-chip communication fabric relying on custom-made on-chip multicast routers [12,13]. The aim of SpiNNaker project is to simulate a billion spiking neurons in real time [14][15][16].…”

Section: Spinnaker Architecturementioning

confidence: 99%

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Khomenko

Germanos

2015

Lecture Notes in Computer Science

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Abstract. Reference passing systems, like mobile and reconfigurable systems are common nowadays. The common feature of such systems is the possibility to form dynamic logical connections between the individual modules. However, such systems are very difficult to verify, as their logical structure is dynamic. Traditionally, decidable fragments of π-calculus, e.g. the well-known Finite Control Processes (FCP), are used for formal modelling of reference passing systems. Unfortunately, FCPs allow only 'global' concurrency between processes, and thus cannot naturally express scenarios involving 'local' concurrency inside a process, such as multicast. In this paper we propose Extended Finite Control Processes (EFCP), which are more convenient for practical modelling. Moreover, an almost linear translation of EFCPs to FCPs is developed, which enables efficient model checking of EFCPs.

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Section: Spinnaker Architecturementioning

confidence: 99%

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Khomenko

Germanos

2015

Lecture Notes in Computer Science

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“…This routing mechanism involves several modules inside the chip and a special look-up table which is maintained by a Packet Router. The key feature of this chip lays on this specialty; by properly configuring the Packet Router, the developer can create an efficient massively distributed computing system [5]. There are several communication protocols available for an application program.…”

Section: Spinnaker Infrastructurementioning

confidence: 99%

Factor Graph Inference Engine on the SpiNNaker Neural Computing System

Sugiarto

Conradt

2014

Artificial Neural Networks and Machine Learning – ICANN 2014

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Abstract. This paper presents a novel method for implementing Factor Graphs in a SpiNNaker neural computing system. The SpiNNaker system provides resources for fine-grained parallelism, designed for implementing a distributed computing system. We present a framework which utilizes available SpiNNaker resources to implement a discrete Factor Graph: a powerful graphical model for probabilistic inference. Our framework allows mapping and routing a Factor Graph on the SpiNNaker hardware using SpiNNaker's event-based communication system. An example application of the proposed framework in a real-world robotics scenario is given and the result shows that the framework can handle computation of 26.14 MFLOPS only in 30.5ms. We demonstrate that the framework easily extends for larger Factor Graph networks in a bigger SpiNNaker system, which makes it suitable for complex and challenging computational intelligence tasks.

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“…LIF or Izhikevich neurons). Current SpiNNaker systems offer 4 chips (64 cores) or 48 chips (768 cores) with each core simulating up to 1000 neurons in real time [5], thereby allowing networks of 64.000 (768.000) spiking neurons. The fast asynchronous communication interface is designed to route neural action potentials from arbitrary neurons to a large number of other neurons.…”

Section: The Spinnaker Neural Network Computing Systemmentioning

confidence: 99%

“…Packets can also carry an optional 32-bit payload. [5]. Communication between chips happens on two unidirectional asynchronous interfaces composed of 7 data lines (plus acknowledge), which are optimized for low energy consumption and fast data transfer rates: static levels on the data lines are meaningless, only transitions of bits encode a value.…”

Section: The Spinnaker Inter-chip Communication Protocol and Interfacementioning

confidence: 99%

Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System

Denk

Llobet-Blandino

Galluppi

et al. 2013

Artificial Neural Networks and Machine Learning – ICANN 2013

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Abstract. Various custom hardware solutions for simulation of neural circuitry have recently been developed, each focusing on particular aspects such as low power operation, high computation speed, or biologically detailed simulations. The SpiNNaker computing system has been developed to simulate large spiking neural circuits in real-time in a network of parallel operating microcontrollers, interconnected by a high-speed asynchronous interface. A potential application area is autonomous mobile robotics, which would tremendously benefit from on-board simulations of networks of tens of thousands of spiking neurons in real-time. Currently, the SpiNNaker hardware circuit boards provide a single Ethernet interface for booting, debug, and input and output of data, which results in a severe bottleneck for sensory perception and motor control signals. This paper describes a small and flexible real-time I/O-hardware interface to connect external devices such as robotic sensors and actuators directly to the fast asynchronous internal communication infrastructure of the SpiNNaker neural computing system. We evaluate performance in terms of package throughput and present a simple application demonstration of a closed loop mobile robot interpreting visual data to approach the most salient stimulus.

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An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator

Cited by 19 publications

References 2 publications

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Modelling and Analysis Mobile Systems Using $$\pi $$ -calculus (EFCP)

Factor Graph Inference Engine on the SpiNNaker Neural Computing System

Real-Time Interface Board for Closed-Loop Robotic Tasks on the SpiNNaker Neural Computing System

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