An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

Tsukada, T.; Hashimoto, Yuta; Sakata, Kohji; Okada, Hiroyuki; Ishibashi, Koji

doi:10.1109/jssc.2004.838010

Cited by 45 publications

(30 citation statements)

References 12 publications

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“…The speed of sample circuits has also been used to characterize mitigation circuits as in [1] where the improvement in CPU speed is used as a metric to determine the effectiveness of a mitigation scheme. Mitigation circuits have further been characterized in terms of the minimum supply voltage or worst case supply dip [2][3] [4], the average dip in supply voltage [4], and peak-to-peak supply voltage [5] [6].…”

Section: Figures Of Meritmentioning

confidence: 99%

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Analysis of power supply noise mitigation circuits

Charania

Chuang

Opal

et al. 2011

2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)

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Power supply noise has become an increasing concern for circuit designers with the recent advances in technology. As a result there has been an introduction of active supply noise mitigation circuits in addition to the currently used passive bypass/decoupling capacitors for on-chip noise suppression. This paper proposes figures of merit for characterizing the various emerging mitigation circuits as well as provides a theoretical and practical analysis of a switched capacitor based active mitigation technique for the CMOS 65 nm technology node.

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Section: Figures Of Meritmentioning

confidence: 99%

“…With increasing levels of supply noise seen on chips, a number of active circuit techniques have emerged in the literature [1] [2][3] [4] [5] [6] [7][8] [9] in an attempt to increase the levels of noise suppression in an area similar to that of passive bypass/decoupling capacitors.…”

Section: Introductionmentioning

confidence: 99%

Analysis of power supply noise mitigation circuits

Charania

Chuang

Opal

et al. 2011

2011 24th Canadian Conference on Electrical and Computer Engineering(CCECE)

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“…Active decoupling capacitor (active decaps) circuit has been introduced in [3] and [4] to suppress the substrate noise in mixed-signal integrated circuits, which employs the Miller effect to boost the effective decap value. Fig.…”

Section: Proposed Double Active-decoupling Techniquementioning

confidence: 99%

A double active-decoupling technique for reducing package effects in a cognitive-radio balun-LNA

Liu

Mak

Zhao

et al. 2011

2011 Asia Pacific Conference on Postgraduate Research in Microelectronics &Amp; Electronics

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“…Accurate modeling and analyzing of substrate coupling is a prerequisite to evaluate the impacts of substrate coupling noise; it also provides parameters for some substrate noise reduction circuits design [13], [16], [17]. Either passive or active methods are applied for substrate coupling noise reduction.…”

Section: Introductionmentioning

confidence: 99%

An Active Guarding Circuit Design for Wideband Substrate Noise Suppression

Chao

Wuen²,

Wen³

2008

IEEE Trans. Microwave Theory Techn.

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In this paper, an active guarding circuit is presented for wideband substrate noise suppression. A feed-forward compensation mechanism is proposed to extend the noise suppression bandwidth and to adjust the amplitude of phase-inversed noise cancellation current by introducing a zero and an amplitude controller. A noise decoupling mechanism is developed to provide a decoupling path and to sense the noise level for generating noise cancellation current. With substrate characterization, parameters of substrate network impedance, decoupling factor, and amplitude of noise cancellation current can be either obtained or determined. The active guarding circuit is implemented in a 90-nm CMOS process based on substrate characterization. The measured substrate noise suppression is better than 9 dB from dc to 250 MHz. The 3-dB suppression bandwidth is effectively extended to 1.2 GHz. The power consumption and circuit area are 2.5 mW and 20 m 41 m, respectively.

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An on-chip active decoupling circuit to suppress crosstalk in deep-submicron CMOS mixed-signal SoCs

Cited by 45 publications

References 12 publications

Analysis of power supply noise mitigation circuits

Analysis of power supply noise mitigation circuits

A double active-decoupling technique for reducing package effects in a cognitive-radio balun-LNA

An Active Guarding Circuit Design for Wideband Substrate Noise Suppression

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