2018 IEEE International Symposium on Circuits and Systems (ISCAS) 2018
DOI: 10.1109/iscas.2018.8351765
|View full text |Cite
|
Sign up to set email alerts
|

An Offset-Canceling Approximate-DFT Beamforming Architecture for Wireless Transceivers

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

0
1
0

Year Published

2019
2019
2023
2023

Publication Types

Select...
3

Relationship

2
1

Authors

Journals

citations
Cited by 3 publications
(2 citation statements)
references
References 13 publications
0
1
0
Order By: Relevance
“…An N -element uniformly-spaced linear antenna array can be used to realize an N -beam multi-beamformer by computing N -element discrete Fourier transforms (DFTs) along the spatial dimension. These computations can be efficiently performed using a spatial Fast Fourier transform (FFT), which can be implemented using both analog as well as digital approaches [88] and reduces the brute force computational complexity of the DFT from O(N 2 ) down to O(N log N ). Moreover, approximate versions of the DFT can be computed with even lower complexity than the FFT, as shown by Cintra, Bayer, and their collaborators [89]- [93].…”
Section: Novel Wideband Multi-beamformers At Low Size Weight Anmentioning
confidence: 99%
“…An N -element uniformly-spaced linear antenna array can be used to realize an N -beam multi-beamformer by computing N -element discrete Fourier transforms (DFTs) along the spatial dimension. These computations can be efficiently performed using a spatial Fast Fourier transform (FFT), which can be implemented using both analog as well as digital approaches [88] and reduces the brute force computational complexity of the DFT from O(N 2 ) down to O(N log N ). Moreover, approximate versions of the DFT can be computed with even lower complexity than the FFT, as shown by Cintra, Bayer, and their collaborators [89]- [93].…”
Section: Novel Wideband Multi-beamformers At Low Size Weight Anmentioning
confidence: 99%
“…Thus, we designed the circuit shown in Fig. 4, which is an enhanced and modified version of the original DCM circuit [37], to realize the 1 : k DCCs required to implement the a-DFT. The main improvements include the use of cascode transistors to reduce systematic mismatch and the use of k successively-switched branches to generate k matched outputs.…”
Section: Dcm and Dynamic Current Copier (Dcc)mentioning
confidence: 99%