An object code compression approach to embedded processors

Yoshida, Yukihiro; Song, Bao-Yu; Okuhata, Hiroyuki; Onoye, Takao; Shirakawa, Isao

doi:10.1145/263272.263349

Cited by 64 publications

(18 citation statements)

References 6 publications

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“…A MIPS processor, "Code Compressed RISC Processor," has been developed [2, 7, and 21] to decompress Huffman encoded instruction cache lines. Some simple compression methods based on dictionaries [1], in which instructions are replaced by indexes into a table have been proposed [23]. More complex dictionary methods, such as arithmetic coding, have been examined [10] [11].…”

Section: Related Workmentioning

confidence: 99%

Profile-driven compression scheme for embedded systems

Waldman

Pinter

2006

Proceedings of the 3rd Conference on Computing Frontiers

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The extensive usage of embedded systems involves running complex applications that require tightly limited resources such as memory and storage. One efficient way to satisfy the resource requirements is to reduce the code size through code compression. Our work describes a software-based code compression scheme that reduces the storage space of a program, which in turn induces a reduction of access time to off-chip memory in SoC embedded architectures. To select those sections of code that are most advantageous for compression, our scheme utilizes profiling information to evaluate and trade off storage space reduction for future run-time overhead. During run-time, the compressed parts are decompressed as necessary into a run-time buffer for execution. Experimental results on the SPEC CPU2000 and MediaBench suites show reduction in code size averaging 18.5%, along with reasonable memory consumption overhead averaging 3.8%, and a reasonable run-time overhead averaging 7.8%.

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Section: Related Workmentioning

confidence: 99%

Profile-driven compression scheme for embedded systems

Waldman

Pinter

2006

Proceedings of the 3rd Conference on Computing Frontiers

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“…The idea of using code compression as a tool for chip size reduction in microprocessors has mostly incited interest in the area of single instruction issue (usually RISC) processors. In addition to that, the code compression can be beneficial to energy as well, because it reduces the energy consumed in reading instructions from memory and communicating them to the processor core [15,22,5,18]. The code compression techniques can be used either when the ISA (Instruction Set Architecture) is specified or not.…”

Section: Introductionmentioning

confidence: 99%

Instruction re-encoding facilitating dense embedded code

Bonny¹,

Henkel²

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Reducing the code size of embedded applications is one of the important constraint in embedded system design. Code compression can provide substantial savings in terms of size. In this paper, we introduce a novel and efficient hardware-supported approach. Our approach investigates the benefits of re-encoding the unused bits (we call them re-encodable bits) in the instruction format for a specific application to improve the compression ratio. Re-encoding those bits may reduce the size of decoding table by more than 37%. We achieve compression ratios as low as 44% (including all overhead that incurs). We have conducted evaluations using a representative set of applications and have applied it to two major embedded processors, namely MIPS and ARM.

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“…In particular, successful attempts were made to limit energy consumption in embedded systems by reducing memory energy requirements through the compression of I-Cache [8] [12] and main program memory [7] [9]. The issue of designing fast and inexpensive HW compression units for processor's machine-code has been extensively investigated in [2] and found its way in some industrial products (e.g., [5] [14]).…”

Section: Previous Workmentioning

confidence: 99%

“…Until recently, information compression techniques were only targeted towards code size reduction [7] [10]. A few of them were adopted with remarkably good results and industrial exploitation (e.g., CodePack [14] and ARM Thumb [5]), but energy optimization was never considered as primary optimization objective, and thus acquired just as a by-product of code size minimization.…”

Section: Introductionmentioning

confidence: 99%

A new algorithm for energy-driven data compression in VLIW embedded processors

Macii¹,

Macii²,

Crudo³

et al.

2003 Design, Automation and Test in Europe Conference and Exhibition

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This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the dominant factors in the SoC energy budget (i.e., main memory access and high throughput global bus). Based on a differential technique, both the new algorithm and the HW compression unit have been developed to efficiently manage data compression and decompression into a high performance industrial processor architecture, under strict real time constraints (Lx-ST200: A 4-issue, 6-stages pipelined VLIW processor with on-chip D and I-Cache). The original Data-Cache line is compressed before write-back to main memory and, then, decompressed whenever Cache refill takes place. An extensive experimental strategy has been developed for the specific validation of the target Lx processor. In order to allow public comparison, we also report the results obtained on a MIPS pipelined RISC processor simulated with SimpleScalar. The two platforms have been benchmarked over Ptolemy and MediaBench programs. Energy savings provided by the application of the proposed technique range from 10% to 22% on the Lx-ST200 platform and from 11% to 14% on the MIPS platform.

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An object code compression approach to embedded processors

Cited by 64 publications

References 6 publications

Profile-driven compression scheme for embedded systems

Profile-driven compression scheme for embedded systems

Instruction re-encoding facilitating dense embedded code

A new algorithm for energy-driven data compression in VLIW embedded processors

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