An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance

Chou, Chung-Cheng; Lin, Zheng-Jun; Tseng, Pei-Ling; Li, Chih-Feng; Chang, Chih‐Sheng; Chen, Wei-Chi; Chih, Yu-Der; Chang, Tsung-Yung Jonathan

doi:10.1109/isscc.2018.8310392

Cited by 74 publications

(33 citation statements)

References 3 publications

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“…Compensating the VT loss by increasing the gate polarity (gate overdrive) leads to increased complexity, reliability issues and more complex voltage management. In [6] [7] [8] [9], the reset gate voltage is raised between 2.4 up to 6V in order to perform a fast reset. The high voltages considered will cause stress in (i) the selected bitcell transistor, (ii) the neighbors bitcells selectors sharing the same BL and WL and in (iii) the near memory array periphery.…”

Section: Polarity Gate (Pg)mentioning

confidence: 99%

“…When used with bipolar RRAM technologies, unipolar MOS selectors cannot perform equally in each polarity and lead to strongly unbalanced programming operations [5] and strongly overdriven selector during reset operation [6] [7] [8] [9], (leading to faster aging of the selector). To overcome this issue, we propose the use of Polarity Controllable Transistors (PCT) such as the multiple independent all-around gate transistors [10] which are opening a new era in microelectronic circuit design.…”

Section: Introductionmentioning

confidence: 99%

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Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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With the continuous scaling of CMOS technology, integrating an embedded high-density non-volatile memory appears to be more and more costly and technologically challenging. Beyond floating-gate memory technologies, bipolar Resistive Random Access Memories (RRAM) appear to be one of the most promising technologies. However, when organized in a 1 or 2-Transistor 1-RRAM (1T1R, 2T1R) architectures, they suffer from large bitcell area, degraded performance and reliability issue during reset operation. The association of multiple-independentgate Polarity Controllable Transistors (PCT) with RRAM overcomes these drawbacks, while providing a dense structure. In this paper, we present two innovative PCT-based bitcells and propose an extensive study of their functionality, physical design considerations and performances in read and write operations compared to CMOS-based 1T1R and 2T1R bitcells. The proposed bitcells outperform the performances of 1T1R and 2T1R bitcells in reset (5× to 105× speed improvement) are competitive in term of area (1.35× to 2.6× area reduction versus 2T1R) and avoid gate overdrive (1.2V versus more than 2V in 1T1R bitcells) thus reducing selector reliability concerns. We also propose an innovative programming strategy which takes advantage of the PCT polarity control and enabling 500× improvement in reset performance. Finally, the proposed bitcells performs 15 to 67% faster than CMOS bitcells in read.

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Section: Polarity Gate (Pg)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Levisse

Gaillardon

Giraud

et al. 2019

IEEE Trans. Nanotechnology

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“…In recent years, resistive random access memory (RRAM) has been regarded as a promising solution with very competitive features for meeting the needed to expanding embedded nonvolatile storage demands [1]- [3]. With advantages such as its simple structure, superior scalability and high compatibility to CMOS processes, RRAM becomes very competitive for various embedded non-volatile memory applications [4]- [6].…”

Section: Introductionmentioning

confidence: 99%

Reset Variability in Backfilled Resistive Random Access Memory and Its Correlation to Low Frequency Noise in Read

Kao

Lin

King

2020

IEEE J. Electron Devices Soc.

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Fast and stable switching between states is one of the key factors for the success resistive random access memory (RRAM) development. In an array, wide reset efficiency variation in RRAM cells is found to link to the characteristics of its low frequency noise (LFN) in bit-cell current. Through Monte Carlo simulation on randomly placing conductive filaments (CF), LFN characteristics correspond to the densities of the CF in the RRAM film. Further correlations between LFN features and the reset efficiency are found. In addition, CF topography are found to change after long term cycling tests. A trimming process is proposed to minimize the impacts of stochastic CF generation, leading to increase reset speed.INDEX TERMS Variability, resistive random access memory, low frequency noise, Monte Carlo simulation, conductive filament.

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“…Emerging non-volatile memories (eNVMs) such as phase change memory (PCM) [4] and resistive random-access memory (RRAM) [5] provide attractive solutions due to multilevel states and higher density. However, the development of eNVMs remains at 22nm [6] or 40nm [7] thus lags behind the logic transistor scaling. Instead, SRAM is a mature embedded memory technology that is available at 7nm and beyond [8].…”

Section: Introductionmentioning

confidence: 99%

Xor-Cim

Huang

Jiang

Peng

et al. 2020

Proceedings of the 39th International Conference on Computer-Aided Design

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An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance

Cited by 74 publications

References 3 publications

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Resistive Switching Memory Architecture Based on Polarity Controllable Selectors

Reset Variability in Backfilled Resistive Random Access Memory and Its Correlation to Low Frequency Noise in Read

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