An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Ikeda, Mitsuo; Kondo, Takeshi; Nitta, Koyo; Suguri, Kazuhito; Yoshitome, Takeshi; Minami, Toshihiro; Naganuma, Jiro; Ogura, Takeshi

doi:10.1145/307418.307445

Cited by 15 publications

(6 citation statements)

References 6 publications

(10 reference statements)

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“…In prior parallel video encoding techniques, such as [4] for MPEG-2 HDTV encoding, video streams are concatenated per picture at the packetized elementary stream (PES) phase, as illustrated in Fig. 1 (a).…”

Section: Multi-chip Approachmentioning

confidence: 99%

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A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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SUMMARY This paper proposes a distributed stream multiplexing architecture for video codec LSIs with multi-chip configuration. This distributed architecture utilizes a built-in media multiplexing unit with an external stream input and inter-chip communication interfaces. Parallel protocol processing, with an autonomous inter-chip control mechanism to mix and concatenate packets through daisy-chained transfer paths, provides a complete multi-chip stream output at the end of the chain. Dispensing with external post-processing devices contributes to both high throughput and downsizing of high-end video codec systems. It is configurable for parallel encoding of super high-resolution video, multi-view/-angled HDTV vision and multiple HDTV programs. The architecture was successfully implemented in a fabricated single-chip MPEG-2 422P@HL codec LSI and utilized for the development of a super high-resolution video codec system.

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Section: Multi-chip Approachmentioning

confidence: 99%

“…Parallel encoding methods for MPEG-2 video have been intensively studied [3], [4], where fragments of video images are transferred to multiple encoders and inter-chip information exchange is performed. Output concatenation and multiplexing, however, continue to be performed by external devices as illustrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

Onishi

Nakamura

Yoshitome

et al. 2008

IEICE Transactions on Information and Systems

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“…This approach is reasonable in terms of cost performance and scalability and has been used in some HDTV CODEC systems that use multiple SDTV CODEC's [6], [8]. We used it when we constructed the SHR CODEC system based on multiple MPEG-2 HDTV CODEC LSIs.…”

Section: Spatially Parallel Codec Systemmentioning

confidence: 99%

A Flexible Video CODEC System for Super High Resolution Video

Yoshitome¹,

Nakamura²,

Naganuma³

et al. 2008

IEICE Transactions on Information and Systems

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SUMMARYWe propose a flexible video CODEC system for superhigh-resolution videos such as those utilizing 4k × 2k pixel. It uses the spatially parallel encoding approach and has sufficient scalability for the target video resolution to be encoded. A video shift and padding function has been introduced to prevent the image quality from being degraded when different active line systems are connected. The switchable cascade multiplexing function of our system enables various super-high-resolutions to be encoded and super-high-resolution video streams to be recorded and played back using a conventional PC. A two-stage encoding method using the complexity of each divided image has been introduced to equalize encoding quality among multiple divided videos. System Time Clock (STC) sharing has also been implemented in this CODEC system to absorb the disparity in the times streams are received between channels. These functions enable highly-efficient, high-quality encoding for super-high-resolution video. key words: super high resolution video, CODEC, 4k × 2k

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“…We evaluated its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability [16,17]. The simulation speed was very fast and more than 600 times faster than compiled HDL simulators using RTL description, and it had sufficient performance for simulating several to several dozen million cycles of practical embedded software within 1 hour.…”

Section: Introductionmentioning

confidence: 99%

Advanced concurrent design environment for multimedia system LSIs

Iwasaki

Ochiai

Naganuma

et al. 2002

Systems & Computers in Japan

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SUMMARYThis paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability. The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and is more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.

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An MPEG-2 video encoder LSI with scalability for HDTV based on three-layer cooperative architecture

Cited by 15 publications

References 6 publications

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

A Distributed Stream Multiplexing Architecture for Multi-Chip Configuration beyond HDTV

A Flexible Video CODEC System for Super High Resolution Video

Advanced concurrent design environment for multimedia system LSIs

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