An Isabelle/HOL Formalisation of the SPARC Instruction Set Architecture and the TSO Memory Model

Abstract

The SPARC instruction set architecture (ISA) has been used in various processors in workstations, embedded systems, and in mission-critical industries such as aviation and space engineering. Hence, it is important to provide formal frameworks that facilitate the verification of hardware and software that run on or interface with these processors. In this work, we give the first formal model for multi-core SPARC ISA and Total Store Ordering (TSO) memory model in Isabelle/HOL.We present two levels of modelling for the ISA: The low-level ISA model, which is executable, covers many features specific to SPARC processors, such as delayedwrite for control registers, windowed general registers, and more complex memory access. We have tested our model extensively against a LEON3 simulation board, the test covers both single-step executions and sequential execution of programs. We also prove some important properties for our formal model, including a non-interference property for the LEON3 processor.The high-level ISA model is an abstraction of the low-level model and it provides an interface for memory operations in multi-core processors. On top of the Z. Hóu

Trace Semantics and Algebraic Laws for Total Store Order Memory Model

“…Two provablyequivalent models of x86-TSO, including an intuitive operational model based on local write buffers and an axiomatic model were presented in [5]. Hóu et al [22] gave the axiomatic TSO model and the operational TSO model on the top of the high-level ISA model and the low-level ISA model respectively. Khyzha and Gotsman [23] formalized the valid executions of the TSO memory model as graphs of memory access events subject to a set of validity axioms, inspired by the definition of C++ memory model [24] .…”

An Executable Formal Model of the VHDL in Isabelle/HOL

“…The project adopts a multi-layer verification approach where we formalise each layer separately and use a refinement-based approach to show that properties proved at the top level are preserved at the lower levels. This work closely connects with the other components of the project such as the formal modelling and verification of verilog [8] and the SPARCv8 instruction set architecture for the LEON3 processor [9], [10], a verification framework for concurrent C-like programs [11], and automated reasoning techniques for separation logic [12]- [14]. For easy integration, these related sub-projects partly determine our software choices such as Isabelle/HOL and hardware choices such as LEON3 and VHDL.…”

A Digital Twin Runtime Verification Framework for Protecting Satellites Systems from Cyber Attacks

“…The other major challenge is the limited processing capacity on board of the satellite, specifically as power is mainly provided from a solar battery. Although modern satellites employ faster CPUs, many models are still significantly slower than consumer desktops [1], [2]. Running formal verification directly on satellites may take up too much computational resource that could have been allocated to communication and other tasks.…”