An investigation of wafer-to-wafer alignment tolerances for three-dimensional integrated circuit fabrication

Warner, K.; Chen, C.; D’Onofrio, Richard; Keast, C.L.; Poesse, S.

doi:10.1109/soi.2004.1391560

Cited by 8 publications

(1 citation statement)

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“…Improved alignment schemes, registration methods, and better instrumentation should permit submicrometer alignment between the device layers [13], perhaps ultimately limited by the thermal flow and flatness characteristics of this methodology.…”

Section: -D Parallel Layering Processmentioning

confidence: 99%

Low-Temperature Polymer-Based Three-Dimensional Silicon Integration

Kim

Xue

Tiwari

2007

IEEE Electron Device Lett.

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We describe a low-temperature polymer-based 3-D integration technique for wafer-scale transplantation of micrometer thick circuit and device layers onto another host wafer. The maximum temperature of this approach is 340 • C. It incorporates a low-k semiconductor compatible dielectric bonding media, employs tools that are readily available within a fabrication environment, and is very simple to implement. Another unique characteristic of the approach is the simultaneous separation of the transplanting layer from the donor assembly with the bonding to the host assembly. Alignment registration of several micrometers between device layers is demonstrated. Electrical results of 3-D inverter circuit along with demonstration of four-device-layer 3-D integrated stack are presented. Index Terms-Silicon-on-insulator (SOI), system-on-chip integration, 3-D IC, 3-D integration.

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Section: -D Parallel Layering Processmentioning

confidence: 99%