An Investigation of Alternative Cache Organizations

Bell, James; Casasent, David; Bell, C. Gordon

doi:10.1109/t-c.1974.223948

Cited by 42 publications

(9 citation statements)

References 4 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The Direct Mapping buffer is a simple and inexpensively organized buffer, and it does not have the overhead of the record keeping associated with a replacement rule. A previous simulation study [5] has shown that simple orgamzations using Direct Mapping buffers can be cost effective on minicomputers. The results derived here lend analyucal support to that viewpoint.…”

Section: A Few General Comparisonsmentioning

confidence: 99%

Performance Analysis of Cache Memories

Rao

1978

J. ACM

View full text Add to dashboard Cite

Using the Independent Reference assumption to model program behavior, the performance of different buffer organizations (Fully Associative, Direct Mapping, Set Associative. and Sector) are analyzed' (1) The expressions for their fault rate are derived To show more explicitly the dependence of the fault rate on the factors that affect it, distribution-free upper bounds on fault rates are computed for the Direct Mapping, Set Associative, and Sector buffers The use of such bounds is illustrated in the case of the Direct Mapping buffer (2) The performance of the buffers for FIFO and Random Replacement are shown to be identical (3) It is possible to restructure programs to take advantage of the basic organization of the buffers The effect of such restructuring is quantified for the Direct Mapping buffer It is shown that the performance of the Direct Mapping buffer under near-optimal restructuring is comparable to the performance of the Fully Associative buffer Further, the effect of this restructuring is shown to be potentially stronger than that of buffer replacement algorithms KEY WORDS AND PHRASES buffer, cache, statistical analysis, performance analysis, program behavior models, paging, page replacement algorithms, program restructuring, fault rate, distribution-free bounds CR CATEGORIES 4 35, 5 42, 6 34, 8 3

show abstract

Section: A Few General Comparisonsmentioning

confidence: 99%

Performance Analysis of Cache Memories

Rao

1978

J. ACM

View full text Add to dashboard Cite

show abstract

“…(Many others have also studied shared and private caches for various multiprocessor architectures. See, for example, [BEL74], [DUB81], [TAN76], [CEN76], [BRI81], [SMI82], [G0083], [FRA84].) In this paper, we are concerned only with private caches and their corresponding schemes.…”

Section: Introductionmentioning

confidence: 99%

Dynamic decentralized cache schemes for mimd parallel processors

Rudolph¹,

Segall²

1984

Proceedings of the 11th Annual International Symposium on Computer Architecture - ISCA '84

114

View full text Add to dashboard Cite

This paper presents two cache schemes for a shared-memory shared bus multiprocessor. Both schemes feature decentralized consistency control and dynamic type classification of the datum cached (i.e. read-only, local, or shared). It is shown how to exploit these features to minimize the shared bus traffic. The broadcasting ability of the shared bus is used not only to signal an event but also to distribute data. In addition, by introducing a new synchronization construct, i.e. the Test-andTest-and-Set instruction, many of the traditional parallel processing "hot spots" or bottlenecks are eliminated. Sketches of formal correctness proofs for the proposed schemes are also presented. It appears that moderately large parallel processors can be designed by employing the principles presented in this paper.

show abstract

“…Few cache studies in the literature have been done for the small cache sizes (less than 2048 bytes of data) that we propose for initial on-chip caches. In 1974, Bell, Casasent, and Bell [3] published results on small caches with single-word (16-bit) blocks and directmapped placement for the DEC PDP-8, using traces of two scientific programs and the PDP-8 Assembler. The miss ratios that they reported are generally higher than we have found, perhaps due to their use of direct mapping.…”

Section: Introductionmentioning

confidence: 99%

Experimental evaluation of on-chip microprocessor cache memories

Hill

Smith

1984

SIGARCH Comput. Archit. News

View full text Add to dashboard Cite

Advances in integrated circuit density are permitting the implementation on a single chip of functions and performance enhancements beyond those of a basic processors. One performance enhancement of proven value is a cache memory; placing a cache on the processor chip can reduce both mean memory access time and bus traffic. In this paper we use trace driven simulation to study design tradeoffs for small {on-chip) caches. Miss ratio and traffic ratio (bus traffic) are the metrics for cache performance. Particular attention is paid to sub-block caches (also known as sector caches), in which address tags are associated with blocks, each of which contains multiple sub-blocks; sub-blocks are the transfer unit. Using traces from two 16-bit architectures (Z8000, PDP-11) and two 32-bit architectures (VAX-11, System/370), we find that general purpose caches of 64 bytes (net size) are marginally useful in some cases, while 1024-byte caches perform fairly well; typical miss and traffic ratios for a 1024 byte (net size) cache, 4-way set associative with 8 byte blocks are: , .489. (These figures are based on traces of user programs and the performance obtained in practice is likely to be less good.) The use of sub-blocks allows tradeoffs between miss ratio and traffic ratio for a given cache size. Load forward is quite useful. Extensive simulation results are presented.

show abstract

An Investigation of Alternative Cache Organizations

Cited by 42 publications

References 4 publications

Performance Analysis of Cache Memories

Performance Analysis of Cache Memories

Dynamic decentralized cache schemes for mimd parallel processors

Experimental evaluation of on-chip microprocessor cache memories

Contact Info

Product

Resources

About