An investigation into crosstalk noise in DRAM structures

Redeker, M.; Cockburn, B.F.; Elliott, D.G.

doi:10.1109/mtdt.2002.1029773

Cited by 39 publications

(43 citation statements)

References 8 publications

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“…We hypothesize, based on past studies and findings, that there may be three ways of interaction.2 First, changing the voltage of a wordline could inject noise into an adjacent wordline through 2At least one major DRAM manufacturer has confirmed these hypotheses as potential causes of disturbance errors. electromagnetic coupling [15,49,55]. This partially enables the adjacent row of access-transistors for a short amount of time and facilitates the leakage of charge.…”

Section: Mechanics Of Disturbance Errorsmentioning

confidence: 99%

“…This anomaly can be explained only if the disturbance effect of opening a row is weaker at 60ns than at 65ns. In general, row-coupling effects are known to be weakened if the wordline voltage is not raised quickly while the row is being opened [55]. The wordline voltage, in turn, is raised by a circuit called the wordline charge-pump [38], which becomes sluggish if not given enough time to "recover" after performing its job.12 When a wordline is raised every 60ns, we hypothesize that the charge-pump is unable to regain its full strength by the end of each interval, which leads to a slow voltage transition on the wordline and, ultimately, a weak disturbance effect.…”

Section: Figure 4 Number Of Errors As the Refresh Interval Is Variedmentioning

confidence: 99%

“…Wordline voltage fluctuations are likely to place the greatest electrical stress on the immediately neighboring rows [49,55]. Reason 2.…”

Section: Modulementioning

confidence: 99%

“…First, a small cell can hold only a limited amount of charge, which reduces its noise margin and renders it more vulnerable to data loss [14,47,72]. Second, the close proximity of cells introduces electromagnetic coupling effects between them, causing them to interact with each other in undesirable ways [14,42,47,55]. Third, higher variation in process technology increases the number of outlier cells that are exceptionally susceptible to inter-cell crosstalk, exacerbating the two effects described above.…”

Section: Introductionmentioning

confidence: 99%

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Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

433

1,019

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Abstract. Memory isolation is a key property of a reliable and secure computing system -an access to one memory address should not have unintended side effects on data stored in other addresses. However, as DRAM process technology scales down to smaller dimensions, it becomes more difficult to prevent DRAM cells from electrically interacting with each other. In this paper, we expose the vulnerability of commodity DRAM chips to disturbance errors. By reading from the same address in DRAM, we show that it is possible to corrupt data in nearby addresses. More specifically, activating the same row in DRAM corrupts data in nearby rows. We demonstrate this phenomenon on Intel and AMD systems using a malicious program that generates many DRAM accesses. We induce errors in most DRAM modules (110 out of 129) from three major DRAM manufacturers. From this we conclude that many deployed systems are likely to be at risk. We identify the root cause of disturbance errors as the repeated toggling of a DRAM row's wordline, which stresses inter-cell coupling effects that accelerate charge leakage from nearby rows. We provide an extensive characterization study of disturbance errors and their behavior using an FPGA-based testing platform. Among our key findings, we show that (i) it takes as few as 139K accesses to induce an error and (ii) up to one in every 1.7K cells is susceptible to errors. After examining various potential ways of addressing the problem, we propose a low-overhead solution to prevent the errors.

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Section: Mechanics Of Disturbance Errorsmentioning

confidence: 99%

Section: Figure 4 Number Of Errors As the Refresh Interval Is Variedmentioning

confidence: 99%

“…Wordline voltage fluctuations are likely to place the greatest electrical stress on the immediately neighboring rows [49,55]. Reason 2.…”

Section: Modulementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors

Kim¹,

Daly²,

Kim³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

433

1,019

View full text Add to dashboard Cite

show abstract

“…It can be used for the bitline and/or wordline schemes of memories, or for busses in general [1][2][3][4][5][6][7]. Figure 1 shows a generic twisting scheme for a large number of interconnect lines that run from left to right.…”

Section: Formal Twisting Notationmentioning

confidence: 99%