An Introduction to Multi-Core System on Chip – Trends and Challenges

Torres, Lionel; Benoit, Pascal; Sassatelli, Gilles; Robert, Michel; Clermidy, Fabien; Puschini, Diego

doi:10.1007/978-1-4419-6460-1_1

Cited by 12 publications

(9 citation statements)

References 39 publications

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“…Multicores are widely used in modern safety critical embedded systems design. Their advantages over super-scalar processor architectures are lower power consumption, higher performance, and lower design complexity [1]. When designing safety critical applications, many non-functional criteria must be addressed.…”

Section: Introductionmentioning

confidence: 99%

“…When designing safety critical applications, many non-functional criteria must be addressed. The most important ones are the total execution time (because these systems must react to inputs within a fixed delay), the reliability (because failures could have fatal consequences), the power consumption (to maximize the autonomy of the system when it operates on a battery), and the temperature (because of its negative influence on processing speed, reliability, and power consumption) [1]- [4]. There are many real-life applications that motivate our study, including satellite systems, portable medical devices, and full authority digital engine control (FADEC) in aircraft.…”

Section: Introductionmentioning

confidence: 99%

“…Considering these four criteria simultaneously during the design phase is very difficult because they are antagonistic [1], [2], [4]- [9]. For instance, the total execution time and reliability are antagonistic because increasing the reliability requires some form of redundancy (be it spatial or temporal), which negatively impacts the execution time.…”

Section: Introductionmentioning

confidence: 99%

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ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

Abdi

Girault

Zarandi

2019

IEEE Trans. Parallel Distrib. Syst.

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We investigate multi-criteria optimization and Pareto front generation. Given an application modeled as a Directed Acyclic Graph (DAG) of tasks and a multicore architecture, we produce a set of non-dominated (in the Pareto sense) static schedules of this DAG onto this multicore. The criteria we address are the execution time, reliability, power consumption, and peak temperature. These criteria exhibit complex antagonistic relations, which make the problem challenging. For instance, improving the reliability requires adding some redundancy in the schedule, which penalizes the execution time. To produce Pareto fronts in this 4-dimension space, we transform three of the four criteria into constraints (the reliability, the power consumption, and the peak temperature), and we minimize the fourth one (the execution time of the schedule) under these three constraints. By varying the thresholds used for the three constraints, we are able to produce a Pareto front of non-dominated solutions. We propose two algorithms to compute static schedules. The first is a ready list scheduling heuristic called ERPOT (Execution time, Reliability, POwer consumption and Temperature). ERPOT actively replicates the tasks to increase the reliability, uses Dynamic Voltage and Frequency Scaling to decrease the power consumption, and inserts cooling times to control the peak temperature. The second algorithm uses an Integer Linear Programming (ILP) program to compute an optimal schedule. However, because our multicriteria scheduling problem is NP-complete, the ILP algorithm is limited to very small problem instances. Comparisons showed that the schedules produced by ERPOT are on average only 10% worse than the optimal schedules computed by the ILP program, and that ERPOT outperforms the PowerPerf-PET heuristic from the literature on average by 33%.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

Abdi

Girault

Zarandi

2019

IEEE Trans. Parallel Distrib. Syst.

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“…The complexity of multi-processor systems-on-chip (MPSoC) computing systems is continuously increasing [1][2][3]. Implementing multiple on-chip processing cores, and relevant memories, the bottleneck of the computing system becomes the inter-processor communication.…”

Section: Introductionmentioning

confidence: 99%

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Gutiérrez¹

2017

JLPEA

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Abstract:To allow fast communication-at several Gb/s-of multimedia content among processors and memories in a multi-processor system-on-chip, a new approach is emerging in literature: Wireless Network-on-Chip (WiNoC). With reference to this scenario, this paper presents the design of the key element of the WiNoC: the antenna. Specifically, a bow-tie antenna is proposed, which operates at mm-waves and can be implemented on-chip using the top metal layer of a conventional silicon CMOS (Complementary Metal Oxide Semiconductor) technology. The antenna performance is discussed in the paper and is compared to the state-of-the-art, including the zig-zag antenna topology that is typically used in literature as a reference for WiNoC. The proposed bow-tie antenna design for WiNoC stands out for its good trade-off among bandwidth, gain, size and beamwidth vs. the state-of-the-art.

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“…Different interconnect structures have been employed in such systems including point to point (P2P) and bus based [6]. Both these architectures were quite useful until we had only few processors connected through them but as the number of processing elements (P.E) increased several issues were spotted and P2P has limited scalability due to increased complexity [7] while, in buses, scalability is restrained due to the fact that by raising the number of processing elements the resulting propagation delay increases [8].…”

Section: Introductionmentioning

confidence: 99%

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

Amin

Shakir

Javed

et al. 2014

International Journal of Reconfigurable Computing

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We are proposing a design methodology for a fault tolerant homogeneous MPSoC having additional design objectives that include low hardware overhead and performance. We have implemented three different FT methodologies on MPSoCs and compared them against the defined constraints. The comparison of these FT methodologies is carried out by modelling their architectures in VHDL-RTL, on Spartan 3 FPGA. The results obtained through simulations helped us to identify the most relevant scheme in terms of the given design constraints.

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An Introduction to Multi-Core System on Chip – Trends and Challenges

Cited by 12 publications

References 39 publications

ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores

Design of a Wideband Antenna for Wireless Network-On-Chip in Multimedia Applications

Low-Cost Fault Tolerant Methodology for Real Time MPSoC Based Embedded System

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