An Integrated Design for Testability and Automatic Test Pattern Generation System: An Overview

Trischler, E.

doi:10.1109/dac.1984.1585796

Cited by 4 publications

(1 citation statement)

References 9 publications

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“…One way how to solve the problem of accessibility is through the structured design techniques like LSSD, Scan Path, Scan/Set logic and Random Access Scan [4, 9, 101. An important role in the VLSI design process is assigned to the testability analysis procedures. They can be provided at two levels: 0 logic design level [8] 0 RT design level [l] The facilities for the DFT automation are often implemented as AI systems [3,5,71.…”

Section: Introductionmentioning

confidence: 99%

I-path analysis

Blatny

Kotásek

Hlavicka³

Proceedings ETC 93 Third European Test Conference

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In this paper a circuit at the register transfer level will be denoted as an R T L circuit. The paper describes a method for extracting the R T L circuit structure from the circuit formal description, the I-path concept is used. The way of representing the RTL circuit structure by a labelled directed graph where nodes represent components and arcs represent connections between them is presented. Labels identifying the component type are attached t o nodes, other labels are also attached t o arcs t o identify attributes of connections. It is shown, how the graph theory algorifhms can be used t o derive the information about the accessibility of carcuit components, a. e. the existence of I-paths between them, and the sequences of control and clock signals which must be generated t o transfer the information along the existing I-paths.

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Section: Introductionmentioning

confidence: 99%