An integrated CAD system for algorithm-specific IC design

Shung, CB; Jain, Rajeev; Rimey, Ken; Wang, E.; Srivastava, Mani; Lettang, E.; Azim, S.K.; Hilfinger, Paul; Rabaey, Jan M.; Brodersen, R.W.

doi:10.1109/hicss.1989.47146

Cited by 15 publications

(7 citation statements)

References 28 publications

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“…4, which plots the measured bus-capacitance as a function of the chip area. The data is obtained from 50 benchmark examples generated using the HYPER synthesis [82] and the LAGER-IV layout generation [99] tools. The close correlation, which exists between area and bus capacitance, is easily captured in a simple piecewise linear model.…”

Section: A the Behavioral Levelmentioning

confidence: 99%

Power conscious CAD tools and methodologies: a perspective

et al. 1995

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Section: A the Behavioral Levelmentioning

confidence: 99%

Power conscious CAD tools and methodologies: a perspective

et al. 1995

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“…A first step is the system developed by David Knapp [22] which allows for more interactive design than most tools. The work described by Thon, Hilfinger, Rabaey, Broderson et al [20], Huang and Despain [23], as well as that by Breternitz and Shen [15], are also steps in the right direction. Ideally, and as illustrated in Fig.…”

Section: Elements Of An Asip Design Environmentmentioning

confidence: 86%

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

Paulin¹,

Liem²,

May

et al. 1995

Journal of VLSI Signal Processing

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Abstract. This paper describes the trends in DSP (Digital Signal Processing) for telecommunications design at Bell Northern Research (BNR) 1 and the tools needed to address them. The paper is in three parts: First, we present the results of a three month survey of DSP design practices at BNR. We briefly describe the characteristics of the designs, as well as the DSP design tools used. However, the emphasis is on the main bottlenecks in the design process, and the tools required to address them in the future. Then, we present a proposal for a next generation DSP design environment for telecommunication applications, based on the survey results. Particular emphasis will be given to code generation, system-level simulation, and behavioral synthesis, the three most requested design tools. Finally, we provide a description of FlexWare, an embedded software development system which is being developed internally. This system addresses one important aspect of this next generation environment, namely design tools for application-specific instruction-set processors (ASIP). FlexWare is composed of two main components: CodeSyn, a retargetable microcode synthesis system; and Insulin, a VHDL-based instruction set simulation system.

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“…The module generator component Paramog ( [Sad95], [Dit95], Figure 1) of SDI is implemented similarly to classical examples ( [Shu89], [Ben93]). Requests are parametrized by data types, bit widths, and area limits, and Paramog offers a selection of possible layouts realizing the specified function.…”

Section: Previous Workmentioning

confidence: 99%

Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs

Koch

1996

Fourth International ACM Symposium on Field-Programmable Gate Arrays

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An integrated CAD system for algorithm-specific IC design

Cited by 15 publications

References 28 publications

Power conscious CAD tools and methodologies: a perspective

Power conscious CAD tools and methodologies: a perspective

DSP design tool requirements for embedded systems: A telecommunications industrial perspective

Structured Design Implementation - A Strategy for Implementing Regular Datapaths on FPGAs

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