2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
DOI: 10.1109/isscc.2002.992137
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An integrated 802.11a baseband and MAC processor

Abstract: An Integrated 802.11a Baseband and MAC ProcessorAn 0.25pm CMOS mixed-signal baseband and MAC processor for the IEEE 802.11a WLAN standard in 0.25~m CMOS occupies 6.8~6.8"~ and contains 4.OM transistors in a 196-pin BGA package. Power consumption for transmit and receive is 326mW and 452mW. Additional data rates up to 108Mb/s are supported. J. S. Thomson---e

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Cited by 49 publications
(31 citation statements)
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“…Contrary to the general belief (e.g., [20]) and to the specification of the Wistron Neweb CM9 network adapter, the SINR required for 802.11g to achieve a packet error rate of 8% at 6Mbps is not merely a few dBs-but as large as 20dB 1 . This means that the interference distance can be as large as 10 times of carrier sensing range (k=12), assuming a free-space propagation model, or 3 times (k=5) assuming a lossy-terrain propagation model.…”
Section: Inherent System Performance Limitationsmentioning
confidence: 71%
“…Contrary to the general belief (e.g., [20]) and to the specification of the Wistron Neweb CM9 network adapter, the SINR required for 802.11g to achieve a packet error rate of 8% at 6Mbps is not merely a few dBs-but as large as 20dB 1 . This means that the interference distance can be as large as 10 times of carrier sensing range (k=12), assuming a free-space propagation model, or 3 times (k=5) assuming a lossy-terrain propagation model.…”
Section: Inherent System Performance Limitationsmentioning
confidence: 71%
“…The first five parameters are derived from the IEEE 802.11 specifications [15]. SIR min is set according to [28] for 10% Packet Error Rate (PER). γ is set to 2 for the free space line of sight case.…”
Section: Numerical Resultsmentioning
confidence: 99%
“…We compare our architecture with three other architectures proposed earlier [18]- [20]. It is to be noted that because of the use of different technologies and implementation strategies adopted for the referenced designs it is extremely difficult to make a fair comparison with these designs.…”
Section: System Integration: Control Strategy and Power Managementmentioning
confidence: 99%
“…The architecture proposed in [18] uses 0.25-m 5-layer CMOS technology with 2.5 V core supply. The power consumptions of the core at 54 Mbps data rate are 219 mW and 203 mW for transmit and receive directions respectively, which are higher than the ones presented in this work.…”
Section: System Integration: Control Strategy and Power Managementmentioning
confidence: 99%