An integrated 12-V electret earphone driver with symmetric Cockcroft-Walton pumping topology for in-ear hearing aids

Tsai, Jen-Huan; Tseng, Chun-Yen; Tseng, Wei-Kai; Shia, Tim K.; Huang, Po-Chiun

doi:10.1109/ipec.2012.6522623

Cited by 6 publications

(1 citation statement)

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“…It makes sense to explore alternate topology besides the popular Dickson CP to reduce cost. In [6], a 3-stage integrated Cockcroft-Walton CP was developed without high voltage stress across internal on-chip MOSCAPs. However, MOSCAP has large parasitics, which limit the efficiency to only 24%.…”

Section: Introductionmentioning

confidence: 99%

A 1V input, 3-to-6V output, integrated 58%-efficient charge-pump with hybrid topology and parasitic energy collection for 66% area reduction and 11% efficiency improvement

Tsai

Wang

et al. 2014

2014 IEEE Asian Solid-State Circuits Conference (A-Sscc)

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This paper presents a low-area, high-efficiency hybrid 6-stage voltage multiplier by cascoding Dickson chargepumps and modified Cockcroft-Walton charge-pumps, and paralleling them with auxiliary charge-pumps. The proposed architecture obtains a good area and efficiency performance without using high-V devices or external capacitors. Implemented in a standard 0.18-μm CMOS process, the prototype provides a wide output range of 3-6V and 30-240μA load from a 1-V supply with an efficiency of 48-58% (52% at 6V). By using on-chip MOS capacitors as internal pumping capacitors, a 66% area reduction is gained. The area shrinks to 0.05mm 2 per 9× interleaved cell. The efficiency loss due to parasitics is compensated by creating auxiliary parasitic pumping paths to collect parasitic energy. With this feed-forward charge-pump, the efficiency increases extra 11%. Higher efficiency is thus measured than most reported on-chip Dickson CPs and cascoded doublers of comparable gain.

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Section: Introductionmentioning

confidence: 99%