An integrated 118.4 to122 GHz low noise phase-locked loop (PLL) in 0.13 µm SiGe BiCMOS technology

Abstract

Design of a PLL based frequency synthesizer which is able to provide signals over the frequency bands 118.4 122 GHz, 59.2 -61 GHz, and 29.6 30.5 GHz is presented in this paper. A fundamental voltagecontrolled oscillator (VCO) and two high speed divide by two frequency divider stages are used to cover all three frequency ranges. The first divider stage is a digital dynamic divider while second stage is a static frequency divider. The measured PLL phase noise is 95 dBc/Hz at an offset of 100 kHz from 30 GHz output. The circuit is fabricated in IHP 0.13 µm SiGe BiCMOS technology with f t and f max of 300 GHz and 500 GHz, respectively. The whole PLL occupies chip area of 0.7 mm 2 . The total DC power consumption of the PLL is 0.93 Watt.