An integer linear programming based routing algorithm for flip-chip design

Abstract

The flip-chip package provides a high chip-density solution to the demand for more I/O pads of VLSI designs. In this paper, we present the first routing algorithm in the literature for the pre-assignment flip-chip routing problem with a pre-defined netlist among pads and wire-width and signal-skew considerations. Our algorithm is based on integer linear programming (ILP) and guarantees to find an optimal solution for the addressed problem. It adopts a two-stage technique of global routing followed by detailed routing. In global routing, it first uses two reduction techniques to prune redundant solutions and create a global-routing path for each net. Without loss of the solution optimality, our reduction techniques can further prune the ILP variables (constraints) by 85.5% (98.0%) on average over a recent reduction technique. The detailed routing applies X-based gridless routing to complete the routing. Experimental results based on five real industry designs show that our router can achieve 100% routability and the optimal global-routing wirelength and satisfy all signal-skew constraints, under reasonable CPU times, while recent related work results in much inferior solution quality.

Flip-chip routing with unified area-I/O pad assignments for package-board co-design

“…Two related works on flip-chip routing only consider the FA routing problem [3] or the PA routing problem [2], but not both together. Furthermore, the work [2] can only handle the flip-chip structure with the I/O pads placed along the die boundary.…”

“…Two related works on flip-chip routing only consider the FA routing problem [3] or the PA routing problem [2], but not both together. Furthermore, the work [2] can only handle the flip-chip structure with the I/O pads placed along the die boundary. Although the work [3] is for the area-I/O flip-chip structure, its tile-based flow-network construction did not consider the PA nets and the positions of I/O pads which can avoid over design.…”

“…Therefore, it ignores the routing constraints from a printed circuit board (PCB). The second kind of RDL routing is the pre-assignment (PA for short) routing problem where the mapping among the I/O pads and the bump pads is pre-defined before routing and cannot be changed [2]. Further, the pre-defined netlist can provide the routing constraints from the PCB.…”

Octilinear redistributive routing in bump arrays

“…Since the number of possible triangulations is exponential, no optimality is guaranteed for the algorithm. An RDL router by integer linear programming (ILP) on a routing graph is proposed in [2], where the routing edges are picked under a series of linear constraints. A network flow algorithm is adopted in [3] to route Manhattan wires on a routing graph.…”

“…A network flow algorithm is adopted in [3] to route Manhattan wires on a routing graph. The problem with [2] and [3] is the inaccuracy of routing capacities with 45° wires. Figure 2 shows a "tile" with different capacities.…”