An Inspector-Executor Algorithm for Irregular Assignment Parallelization

Arenaz, Manuel; Touriño, Juan; Doallo, Ramón

doi:10.1007/978-3-540-30566-8_4

Cited by 16 publications

(12 citation statements)

References 11 publications

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“…Control-flow irregularity and memory-access irregularity are the two major types of irregularity that exist in programs. There has also been work done on run-time techniques, such as inspector/executor methods, for evaluating parallel irregular computations and reordering/reassigning the operations to remove data dependence conflicts and increase load balance [1]. The amount of static optimization that can be achieved in irregular computations is often limited due to data dependencies that can only be determined at run-time.…”

Section: Related Workmentioning

confidence: 98%

A scalable, efficient scheme for evaluation of stencil computations over unstructured meshes

King

Kirby

2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

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Stencil computations are a common class of operations that appear in many computational scientific and engineering applications. Stencil computations often benefit from compiletime analysis, exploiting data-locality, and parallelism. Postprocessing of discontinuous Galerkin (dG) simulation solutions with B-spline kernels is an example of a numerical method which requires evaluating computationally intensive stencil operations over a mesh. Previous work on stencil computations has focused on structured meshes, while giving little attention to unstructured meshes. Performing stencil operations over an unstructured mesh requires sampling of heterogeneous elements which often leads to inefficient memory access patterns and limits data locality/reuse. In this paper, we present an efficient method for performing stencil computations over unstructured meshes which increases data-locality and cache efficiency, and a scalable approach for stencil tiling and concurrent execution. We provide experimental results in the context of post-processing of dG solutions that demonstrate the effectiveness of our approach.

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Section: Related Workmentioning

confidence: 98%

A scalable, efficient scheme for evaluation of stencil computations over unstructured meshes

King

Kirby

2013

Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis

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“…A key aspect is that variables written within the access phase do not escape its scope, meaning that no writes to globally visible data are allowed (i.e. global variables and function arguments 3 , henceforth referred to as "globals" for brevity), since each loop slice is re-executed by the execute version, which performs the writes. Consequently, the compiler must ensure that globals are correctly identified and no updates are performed within the access phase.…”

Section: Access Phase Generationmentioning

confidence: 99%

“…Generating skeleton phases derived from the original code resembles techniques such as inspector-executor [3,5,35,36,43] and helper thread [23,34,45] methods. Inspector-executor techniques [3,5,35,36,43] rely on the concept of running an inspector version aimed to instrument and analyze the code and typically includes extra code to process the collected information.…”

Section: Related Workmentioning

confidence: 99%

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Multiversioned decoupled access-execute: the key to energy-efficient compilation of general-purpose programs

Koukos

Ekemark

Zacharopoulos

et al. 2016

Proceedings of the 25th International Conference on Compiler Construction

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Computer architecture design faces an era of great challenges in an attempt to simultaneously improve performance and energy efficiency. Previous hardware techniques for energy management become severely limited, and thus, compilers play an essential role in matching the software to the more restricted hardware capabilities. One promising approach is software decoupled access-execute (DAE), in which the compiler transforms the code into coarsegrain phases that are well-matched to the Dynamic Voltage and Frequency Scaling (DVFS) capabilities of the hardware. While this method is proved efficient for statically analyzable codes, generalpurpose applications pose significant challenges due to pointer aliasing, complex control flow and unknown runtime events. We propose a universal compile-time method to decouple generalpurpose applications, using simple but efficient heuristics. Our solutions overcome the challenges of complex code and show that automatic decoupled execution significantly reduces the energy expenditure of irregular or memory-bound applications and even yields slight performance boosts. Overall, our technique achieves over 20% on average energy-delay-product (EDP) improvements (energy over 15% and performance over 5%) across 14 benchmarks from SPEC CPU 2006 and Parboil benchmark suites, with peak EDP improvements surpassing 70%.

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“…At run-time, wavefronts of concurrently executable loop iterations are identified and the loop iterations are reordered for increased parallelism. A similar approach has been taken also in [Arenaz et al 2004] where a loop with irregular assignment computations contains loop-carried output data dependencies that can only be detected at run-time. A load-balanced method based on the inspector-executor model is proposed to parallelize this loop pattern.…”

Section: Related Design Approachesmentioning

confidence: 99%

System-scenario-based design of dynamic embedded systems

Gheorghita

Palkovic²,

Hamers

et al. 2009

ACM Trans. Des. Autom. Electron. Syst.

131

115

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Document VersionPublisher's PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publicationCitation for published version (APA): Gheorghita, S. V., Palkovic, M., Hamers, J., Vandecappelle, A., Mamagkakis, S., Basten, T., ... Bosschere, . System scenario based design of dynamic embedded systems. (ES reports; Vol. 2007-06). Eindhoven: Technische Universiteit Eindhoven. General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim. In the past decade, real-time embedded systems have become much more complex due to the introduction of a lot of new functionality in one application, and due to running multiple applications concurrently. This increases the dynamic nature of today's applications and systems, and tightens the requirements for their constraints in terms of deadlines and energy consumption. State-of-theart design methodologies try to cope with these novel issues by identifying several most used cases and dealing with them separately, reducing the newly introduced complexity. This paper presents a generic and systematic design-time/run-time methodology for handling the dynamic nature of modern embedded systems, which can be utilized by existing design methodologies to increase their efficiency. It is based on the concept of system scenarios, which group system behaviors that are similar from a multi-dimensional cost perspective, such as resource requirements, delay, and energy consumption, in such a way that the system can be configured to exploit this cost similarity. At design-time, these scenarios are individually optimized. Mechanisms for predicting the current scenario at run-time and for switching between scenarios are ...

show abstract

An Inspector-Executor Algorithm for Irregular Assignment Parallelization

Cited by 16 publications

References 11 publications

A scalable, efficient scheme for evaluation of stencil computations over unstructured meshes

A scalable, efficient scheme for evaluation of stencil computations over unstructured meshes

Multiversioned decoupled access-execute: the key to energy-efficient compilation of general-purpose programs

System-scenario-based design of dynamic embedded systems

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