2010 Asia-Pacific International Symposium on Electromagnetic Compatibility 2010
DOI: 10.1109/apemc.2010.5475881
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An innovative FPGA internal core clock jitter prediction methodology

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“…It can be seen that the low mixer 'amplifies' the phase difference between two signals of the same frequency. Since the local oscillator signal of the mixing circuit comes from the PLL output signal of FPGA and the output signal of PLL has slight jitter [29,30], the edge of the output signal after mixing with only one D-flip-flop will inevitably generate burrs. In order to eliminate the burr caused by jitter, we introduce a digital buffing circuit based on the mixing circuit to construct a complete lower mixer, as shown in figure 5.…”
Section: Principle Of Pulse Laser Phase Rangingmentioning
confidence: 99%
“…It can be seen that the low mixer 'amplifies' the phase difference between two signals of the same frequency. Since the local oscillator signal of the mixing circuit comes from the PLL output signal of FPGA and the output signal of PLL has slight jitter [29,30], the edge of the output signal after mixing with only one D-flip-flop will inevitably generate burrs. In order to eliminate the burr caused by jitter, we introduce a digital buffing circuit based on the mixing circuit to construct a complete lower mixer, as shown in figure 5.…”
Section: Principle Of Pulse Laser Phase Rangingmentioning
confidence: 99%