An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs

Gimenez, Salvador Pinillos; Correia, Marcello M.; Neto, Enrico D.; Silva, Cristina R.

doi:10.1109/led.2015.2437716

Cited by 27 publications

(19 citation statements)

References 9 publications

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“…This can be proven by reference [28], which has shown that the gate capacitance of an ellipsoidal layout style for MOSFET (EM) is around 11% greater than the one found in its conventional MOSFET (CM) counterpart in room temperature, because its PN junctions length between the drain/source and channel regions are higher, considering both devices with the same W and bias conditions. However, the RON of the EM is 65% remarkably smaller than that those found in its CM counterpart, and therefore, the τ of the EM is significantly smaller (61%) than the one observed in its CM counterpart in room temperature [28].…”

Section: On-state Resistancementioning

confidence: 97%

“…The gain provided by the octagonal layout style for MOSFET in RON are also discussed in the following references regarding numerical simulations and experimental results in room temperature [24,25] and radiation environment [40,41]. Making an analogy with the study of reference [28], it possible to predict that the delay time constant (τ = RON.CGS, which CGS is gate capacitance) of the OSM tends to be smaller than the one found in its RSM counterpart, regarding that both devices present the same W, and bias conditions. This can be proven by reference [28], which has shown that the gate capacitance of an ellipsoidal layout style for MOSFET (EM) is around 11% greater than the one found in its conventional MOSFET (CM) counterpart in room temperature, because its PN junctions length between the drain/source and channel regions are higher, considering both devices with the same W and bias conditions.…”

Section: On-state Resistancementioning

confidence: 99%

“…These new effects are: LCE, PAMDLE, DEPAMBBRE [14][15][16][17][18][19] that are able to boost its electrical performance. Some examples of this approach are the Diamond [14][15][16][17][18][19][20][21][22], Octo [23][24][25][26][27], Ellipsoidal [28] and Fish [29] The Octo layout style for MOSFETs was specially invented in order to further boost the Electrostatic Discharge (ESD) tolerance and increase the breakdown voltage (BVDS) as compared to those one found in the Diamond (hexagonal gate shape) layout style. The same effects found (LCE, PAMDLE and DEPAMBBRE) in the Diamond SOI MOSFET also exist in the OSM structure, in which the LCE in the OSM structure is more pronounced, because in this case, it is possible to find a higher resultant longitudinal electric field (LEF).…”

Section: Introductionmentioning

confidence: 99%

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Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Galembeck

Flandre

Renaux

et al. 2019

JICS

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This present paper performs an experimental comparative study of the main digital parameters and figures of merit of the octagonal layout style for the planar Silicon-On-Insulator (SOI) Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET), named OCTO SOI MOSFETs (OSM) in comparison with the typical rectangular one at high temperature environments. The devices were manufactured with the 1 mm SOI (CMOS) technology. The results demonstrate that the OSM is capable of keeping active the Longitudinal Corner Effect (LCE), the PArallel Connection of MOSFETs with Different Channel Lengths Effect (PAMDLE) and the Deactivate the Parasitic MOSFETs of the Bird’s Beak Regions Effect (DEPAMBBRE) at high temperature conditions. Therefore, the OSM is able to continue to have a better electrical performance than the one found in the rectangular SOI MOSFET (RSM) counterparts, regarding the same gate areas and bias conditions. To illustrate, its on-state drain current (ION) and off-state drain current (IOFF) are respectively 186% higher and 64% smaller in relation to its RSM counterparts at high temperature conditions.

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Section: On-state Resistancementioning

confidence: 97%

Section: On-state Resistancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Galembeck

Flandre

Renaux

et al. 2019

JICS

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“…Deve-se ressaltar que uma possível alternativa para a implementação de MOSFETs, que não adiciona qualquer custo para o atual processo de fabricação de CIs CMOS, é a denominada de "Engenharia de Junção PN entre as regiões de Dreno-Canal e Canal-Fonte do MOSFET", que se refere ao uso de novos e diferentes estilos de leiautes de porta para a implementação de transistores que possuem formatos de porta não retangulares, ou seja, diferentemente dos MOSFETs convencionais [20]. Alguns exemplos dessas estruturas de leiaute não convencionais de porta são: SOI MOSFETs de porta em formato de Anel Circular (CGSMs) [21], [22], MOSFETs do tipo Wave (formato de porta semelhante a letra "S") [23], [24], [25] do tipo Fish [26], [27], do tipo Diamante [28], [29], do tipo Octogonal [30] e do tipo elipsoidal [31].…”

Section: 212 Introduçãounclassified

Estudo do casamento entre MOSFETs implementados com geometrias de porta não convencionais em ambientes de radiações de raios X

Peruzzi¹

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This doctoral thesis illustrates the studies of the variability and mismatch between "N" type MOSFET devices (nMOSFETs) with hexagonal (DnM), octagonal (OnM) and rectangular (CnM) gate geometry, considering four different types of bias of these nMOSFETs during the ionizing radiation procedure X-ray: I- without electrical bias or with all terminals (source, door, drain and substrate) open (Floating); II- with electrical bias of the devices in the operating state of “on-state” or “closed-switch” (On-state); III- with bias of the devices in the condition of analogue operation or operating as an amplifier (Analog); IV- with device bias in the state-off or “open-switch” operating condition (Off-state). Considering the Floating bias, during the Xray ionizing radiation procedure, it appears that DnMs with an a angle of 90° reduce the mismatch between devices by 40.7% for the threshold voltage (VTH) and 56.8% for the subthreshold slope (SS), respectively, in comparison to the values found in the CnMs counterparts. Considering the On-state bias during the procedure of X-ray ionizing radiation, it is observed that OnMs with an a angle of 90° and a 50% “c” factor improve the matching between devices by 57.4% for VTH and 54.9% for SS compared to those found in CnM counterparts. In the Analog and Off-state bias during the X-ray ionizing radiation procedure, the DnMs and OnMs showed a better matching between devices compared to those obtained with the CnMs counterparts and with a 95% accuracy level. During the procedure of X-ray ionizing radiation in Floating mode, the maximum total ionizing dose (TID) used was in the order of up to 4.5 Mrad. In addition, during ionizing X-ray radiation procedures in On-State, Off-State and Analog modes, the maximum TIDs used were 200 krad for On-State and Analog modes and 20 krad for Off-State mode. Therefore, the Diamond and Octo layout styles can be considered as alternative layout strategies for the implementation of MOSFETs in order to enhance their tolerances to ionizing X-ray radiation, aiming at applications in integrated circuits (ICs) implemented with Complementary Metal-Oxide-Semiconductor (CMOS) manufacturing technology

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“…Dessa forma, ao aumentar a velocidade média de deriva dos portadores móveis do canal ( = * ⃗ // , sendo v a velocidade média de deriva dos portadores do canal, μ a mobilidade dos portadores móveis porta retangular de diferentes comprimentos de canal e com larguras de canal infinitesimais. Assim sendo, a corrente entre dreno e fonte tende a fluir mais pelas bordas do dispositivo, onde existem os MOSFETs com menores comprimentos de canal[13][29][30]. Correspondente circuito elétrico equivalente de um DM.…”

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Distorção harmônica entre os MOSFETs implementados com os estilos de leiaute do tipo diamante híbrido e convencionais

Aoyama¹

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Nowadays there are different researches fronts (use of new transistor structures, new materials, etc.) both in educational institutions and research centers, that aim to reduce the size of the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET), then to keep the socalled Moore Law. An innovative approach has been recently proposed that does not add additional costs to the current manufacturing processes of Planar Complementary MOS Integrated Circuits (ICs), called unconventional gate layout MOSFETs, which are able to enhance their electrical performance in analog applications over the equivalent rectangular gate geometry MOSFET. This master thesis aims to conduct a comparative experimental study of the behavior of the total harmonic distortion normalized by the voltage gain (THD/Av) in the Hybrid Diamond type gate layout MOSFET (Composed by the parallel association of 3 MOSFETs: in the center a MOSFET of Diamond type and two rectangular gate MOSFETs) compared to the conventional rectangular gate geometry MOSFET (CM), as it is a very important figure of merit in analog applications. Hybrid Diamond MOSFET (HDM) was developed due to the limitations of the manufacturing process of more sophisticated ICs that do not allow the gate region to be defined orthogonally to the active transistor region. The MOSFETs used in this research project were manufactured using commercial process TSMC's 0.18 μm CMOS Bulk via IMEC's Mini @ sic university program. The Integral Function Method was used to perform the THD/Av study of MOSFETs. This method uses only the direct current characteristic curve of the MOSFET operating in the saturation region (this curve is the current between the drain and the source as a function of the voltage between the gate and the source). One of the main results obtained by this research project shows that HDM with an alpha (α) angle of 45 ° is able to reduce THD/Av by about 6.4 dB for a gate overvoltage of 600 mV when Compared to CM, this is because the Hybrid Diamond MOSFET with angle α equal to 45 ° had a higher intrinsic voltage gain than CM, since THD/Av is strongly dependent on the voltage gain of these devices.

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An Innovative Ellipsoidal Layout Style to Further Boost the Electrical Performance of MOSFETs

Cited by 27 publications

References 9 publications

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Digital Performance of OCTO Layout Style on SOI MOSFET at High Temperature Environment

Estudo do casamento entre MOSFETs implementados com geometrias de porta não convencionais em ambientes de radiações de raios X

Distorção harmônica entre os MOSFETs implementados com os estilos de leiaute do tipo diamante híbrido e convencionais

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