An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS

Erbagci, Burak; Akkaya, Nail Etkin Can; Erbagci, Cagri; Mai, Ken

doi:10.1109/esscirc.2019.8902789

Cited by 1 publication

(1 citation statement)

References 7 publications

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“…In this direction, B. Erbagci et al, proposed an FPGA design in which a PUF is used to One-Time-Pad (OTP) encrypt the bitstream configuration data. Their work has been presented in two publications, one in 2015 [130] and one in 2019 [131]. The design requirements are the following:…”

Section: ) Hardware Entanglementmentioning

confidence: 99%

FPGA Bitstream Modification: Attacks and Countermeasures

Moraitis

2023

IEEE Access

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Advances in FPGA technology in recent years have resulted in an expansion of its usage in a very wide spectrum of applications. Apart from serving the traditional prototyping purposes, FPGAs are currently regarded as an integral part of embedded systems used in many industries, including communication, medical, aerospace, automotive, and military. Moreover, the emerging trend of AI has found FPGAs to be at the technological forefront with their use as deep learning acceleration platforms. The demand for FPGAs has grown to the point that major companies (e.g. Amazon) are offering cloudbased access to FPGAs, known as FPGA-as-a-Service. In many applications, FPGAs handle sensitive data and/or host cryptographic algorithm implementations. These FPGAs are not always located in a tamperresistant environment, which makes their security a major concern, especially in light of the ever-growing number of publications demonstrating effective attacks specifically tailored to exploit the physical traits of FPGA implementations. In this survey, we cover the subset of those attacks that involve tampering with the FPGA configuration bitstream. We start by discussing how the FPGA vendors attempt to protect their products and how malicious parties try to overcome this protection. We then proceed to present the different bitstream modification attacks that can be found in the literature organized according to their targets. Finally, we present various countermeasures that can be deployed, drawing on bibliographic references from works specifically focused on FPGA bitstream protection, as well as those initially proposed for different purposes or devices that can be adapted for bitstream protection.

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Section: ) Hardware Entanglementmentioning

confidence: 99%

FPGA Bitstream Modification: Attacks and Countermeasures

Moraitis

2023

IEEE Access

View full text Add to dashboard Cite

show abstract

An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS

Cited by 1 publication

References 7 publications

FPGA Bitstream Modification: Attacks and Countermeasures

FPGA Bitstream Modification: Attacks and Countermeasures

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