An Inclusive Structural Analysis on the Design of 1.2kV 4H-SiC Planar MOSFETs

Abstract

A detailed structural analysis of 1.2 kV 4H-SiC MOSFETs with accumulation mode channel is reported in this paper. 1.2 kV SiC MOSFETs with a variety of cell designs were fabricated and compared with respect to the output and transfer characteristics, and blocking behaviors. All the design rules, such as channel length, JFET width, contact openings, gate-to-source overlap, and cell pitch were investigated to clearly provide the quantitative impact on the static performances. 2D-simulation was also conducted to support experimental results. As a result, it turned out that the channel length is the most determining factor for the specific on-resistance, resulting in 0.364 mΩ-cm 2 increase per 0.1 μm increase in the channel length. However, the channel potential is also largely dependent on the channel length such that the leakage current tends to increase with short channel design. The enhanced doping in the JFET region with a current spreading layer (CSL) is essential for achieving a narrower JFET width, which satisfies all static performances, as well as device reliability and ruggedness. Methods to further improve the trade-off characteristics using other design aspects are discussed in this paper.

Implant Straggle Impact on 1.2 kV SiC Power MOSFET Static and Dynamic Parameters

“…This was the basis for the actual mask design used for these devices as illustrated in Fig. 1(a), as also commonly used in other published optimized devices [2][9] [15]. However, the minimum value for Ron,sp of 2.3 mΩcm 2 is much (> 2x) smaller than the measured value given in Table I for the fabricated devices.…”

“…In addition, the impact of lateral straggle of the P + shielding region on the dynamic characteristics of the SiC power MOSFET was not discussed in the previous publications [13] [15]. The analysis presented in this paper shows a substantial reduction in the gate-drain capacitance and the gate-drain charge due to the implant straggle of the P + shielding region that is favorable for obtaining faster transients…”

“…It has been shown by analytical modelling that the specific on-resistance has a minimum value with varying JFET width [11][24]. This optimization was performed when designing the 1.2 kV SiC power MOSFETs for this paper before fabrication without taking straggle LSP+ into account, as commonly done in previously reported devices in the literature [2][9] [15].…”

“…The authors state that the straggle of the P-well is significant for their 13 kV devices due to the low drift region doping level, unlike in the case of 1.2 kV SiC power MOSFETs with a JFET width of 1.4 m. A detailed analysis with experimental data was recently published on the impact of changing the channel length and JFET width for accumulation-channel 1.2 kV SiC power MOSFETs with 50 nm gate oxide thickness [15]. Consideration of the impact of ion-implant straggle of the P-well on device performance and cell optimization is not mentioned in that paper.…”

Channel Design Optimization for 1.2-kV 4H-SiC MOSFET Achieving Inherent Unipolar Diode 3rd Quadrant Operation

“…The devices were fabricated at Analog Devices, Inc. (ADI) fabrication facility in Hillview, San Jose, CA, USA [8,9]. A 10 µm thick drift layer with N-epi doping concentration of about 8×10 15 cm −3 on a 6-inch, N+ 4H-SiC substrate was used for the fabrication of 1.2 kV MOSFETs.…”