An improved residue number system digital-to-analog converter

Soderstrand, M.A.; Vernia, Cecilia; Chang, Jui-Hua

doi:10.1109/tcs.1983.1085311

Cited by 64 publications

(15 citation statements)

References 5 publications

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“…If n processing units perform the computation, the processing speed will be n times faster. So, RNS is studied with a view to its application in the areas where fast and parallel processing methods are required [1][2][3][4]. Digital signal processing is one such area.…”

Section: Introductionmentioning

confidence: 99%

Cox-Rower Architecture for Fast Parallel Montgomery Multiplication

Kawamura

Koike

Sano

et al. 2000

Lecture Notes in Computer Science

115

279

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Abstract. This paper proposes a fast parallel Montgomery multiplication algorithm based on Residue Number Systems (RNS). It is easy to construct a fast modular exponentiation by applying the algorithm repeatedly. To realize an efficient RNS Montgomery multiplication, the main contribution of this paper is to provide a new RNS base extension algorithm. Cox-Rower Architecture described in this paper is a hardware suitable for the RNS Montgomery multiplication. In this architecture, a base extension algorithm is executed in parallel by plural Rower units controlled by a Cox unit. Each Rower unit is a single-precision modular multiplier-and-accumulator, whereas Cox unit is typically a 7 bit adder. Although the main body of the algorithm processes numbers in an RNS form, efficient procedures to transform RNS to or from a radix representation are also provided. The exponentiation algorithm can, thus, be adapted to an existing standard radix interface of RSA cryptosystem.

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Section: Introductionmentioning

confidence: 99%

Cox-Rower Architecture for Fast Parallel Montgomery Multiplication

Kawamura

Koike

Sano

et al. 2000

Lecture Notes in Computer Science

115

279

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“…Numerous techniques have been discussed for these operations using the Chinese remainder theorem (CRT) and the mixed radix conversion (MRC) [6-131. The problems associated with the MRC are complex, and the problem associated with the C R T approach is the requirements of modulo M adders. In light of various techniques in , t w o efficient fractional techniques based on the CRT were proposed [6,9]. The fractional approach presented in [6] is faster and requires the least hardware of all the methods so far considered, but the basic draw back of this method is that a very little error will be introduced in the conversion process.…”

Section: Introductionmentioning

confidence: 99%

“…In light of various techniques in , t w o efficient fractional techniques based on the CRT were proposed [6,9]. The fractional approach presented in [6] is faster and requires the least hardware of all the methods so far considered, but the basic draw back of this method is that a very little error will be introduced in the conversion process.…”

Section: Introductionmentioning

confidence: 99%

“…An excellent review of the concept and properties of the core function was presented in [ 5 ] . In this p a p e r , w e h a v e p r e s e n t e d the h a r d w a r e implementation of residue to binary conversion using the c o r e function and compared the hardware requirements and the conversion time with other three techniques proposed in [6,7,8] at the functional level. In the following section a brief review of t h e residue arithmetic is p r e s e n t e d .…”

Section: Introductionmentioning

confidence: 99%

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Implementation Issues on the Decoding Algorithms of RNS to Binary Conversion

Krishnan¹

1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990.

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Ab str actResidue to binary converters are very essential for residue number system (RNS) digital signal processing architectures. In this paper we have presented a hardware implementation of RNS to binary decoder using a new technique called core function. In order to evaluate the efficiency of the core function approach, we have considered three other techniques which are considered to be the most efficient techniques for the residue eo binary conversion. The results have been tabulated for the above three techniques and the newly proposed core function technique in terms of number of computational elements and other associated hardwares, the conversion time and the accuracy.

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“…nowed techniques will &her use (SRT conversion (perhaps with special binary ring mapping strategies or direct mod M adders nsing binary representation [5] or MRC techniques with possibie scaling to a subset of 2 moduli where one of them is a power of two 171. MRC binary conversion requiring larger dynamic range can involve repeated base extension to a power of two modulus.…”

mentioning

confidence: 99%

The Modulus Replication RNS (MRRNS): A Comparative Study

Wigley¹,

Jullien²,

Miller³

1990 Conference Record Twenty-Fourth Asilomar Conference on Signals, Systems and Computers, 1990.

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There have been several recent initiatives to use computations on finite polynomial rings as a tool for evaluating digital signal processing algorithms. A technique was recently introduced, by the authors [9], that allows a direct mapping from the bit pattern of the input numbers to the polynomial coefficients. The mapping strategy is simple, and some of the magnitude information of the resulting computations is preserved in the resulting finite ring operations. This is in contrast to the use of a standard residue number system where magnitude information requires invoking the Chinese Remainder Theorem (or some mixed radix counterpart) across the entire dynamic range of the calculation. Disadvantages of the technique are associated with the relatively large redundancy required in the finite ring computational hardware compared to that required for nonredundant integer calculations (binary, RNS etc.). This paper performs a comparative study of the RNS and MRRNS techniques to show that this redundancy in computational hardware is adequately compensated by the simplicity in mapping, scaling and redundancy considerations for WSI implementation.

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An improved residue number system digital-to-analog converter

Cited by 64 publications

References 5 publications

Cox-Rower Architecture for Fast Parallel Montgomery Multiplication

Cox-Rower Architecture for Fast Parallel Montgomery Multiplication

Implementation Issues on the Decoding Algorithms of RNS to Binary Conversion

The Modulus Replication RNS (MRRNS): A Comparative Study

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