An improved quad Itoh-Tsujii algorithm for FPGAs

Abstract

In this paper, we propose an improved quad Itoh-Tsujii algorithm to compute multiplicative inverse efficiently on Fieldprogrammable gate-arrays (FPGA) platforms for binary fields generated by irreducible trinomials. Efficiency is obtained by eliminating the precomputation steps required in conventional quad-ITA (QITA) scheme. Experimental results show that the proposed architecture improves the performance on FPGAs compared to existing techniques.

High‐performance and high‐speed implementation of polynomial basis Itoh–Tsujii inversion algorithm over GF(2 m )

“…As seen in Table 7 the proposed method for GF(2 193 ) has 2.3, 6, 4.2, 15, 26, 46 and 62% higher speed in computation time and 35, 40, 54, 59 and 48%, two and a half times and three times better performance compared with [8, 6, 5, 4, 7, 3, 2] on Virtex‐E FPGA, respectively.…”

“…Therefore, the number of required multiplications is reduced effectively, because the complexity is logarithmic rather than linear. The hardware implementations of the inversion operation in the literature often use the Itoh–Tsujii algorithm; see for example [1–9, 12]. Guajardo and Paar [13] presented an improved and general version of the Itoh–Tsujii algorithm over polynomial basis for all values of m .…”

“…In [5], a cascaded quad‐root block in parallel with a circuit for exponentiation by 2 97 is used to compute inversion. In [6] by eliminating the pre‐computation steps, an improved quad‐ITA for fields generated by irreducible trinomials is presented. In [7] in order to obtain the best performance of the algorithm on FPGA platforms a theoretical model of the ITA is presented.…”

Efficient hardware structure for extended Euclidean‐based inversion over

“…The comparison is based on parameters such as area consumption, CPD, number of clock cycles and computation time. In Table 5, works [14][15][16][17][18]20] are implemented based on ITA and work [10] is based on the EEA. Inversion architecture in the works [14][15][16][17] is constructed by one field multiplier, several multiplexers with m-bit inputs, squarer blocks (or exponentiation by power of 2 blocks), several m-bit registers and a control unit.…”

“…In recent years, different hardware implementations of the field inversion over F 2 m are presented in literature [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The works [2][3][4][5][6][7][8][9][10][11][12][13][14][15] are implemented in polynomial basis (PB).…”