An improved low offset latch comparator for high-speed ADCs

Abstract

This paper presents a new high-speed and low offset latch comparator. The proposed offset compensation technique for latch comparator enables the preamplifier design relaxation for high-speed and high-resolution analog-to-digital converters. Employing the negative resistance of regeneration latch to enhance the comparator gain in input tracking phase is the key idea to reduce the latch input referred offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 lm CMOS process show that equivalent input referred offset voltage is 200 lV at 1 sigma while it was 26 mV at 1 sigma before offset cancellation. The comparator dissipates 600 lW from a 1.8 V supply while operating in 500 MHz clock frequency.

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

“…The track and latch comparator structure is shown in Figure 4 . Figure 4 is subdivided into two different blocks, where Figure 4(a) design is constructed with an input differential pair; a regenerative latch and a regeneration control switch [16] .…”

An Improved Low-Offset and Low-Power Design of Comparator for Flash ADC

“…In flash ADCs, comparators take quite important roles, especially. Flash ADCs are getting higher speed, and lower power consumption, which compels the comparator to have better performance to meet the strict requirement [1]. In general, there are several kinds of comparators such as comparators using hysteresis, switch capacitor comparators, regenerative comparators and so on, in used [2].…”