An Improved Hardware Implementation of the Grain Stream Cipher

Mansouri, Shohreh Sharif; Dubrova, Elena

doi:10.1109/dsd.2010.49

Cited by 17 publications

(11 citation statements)

References 8 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Grain-80, like other FSR-based stream ciphers, has characteristics that make it ideal for the transformation suggested in this paper: it targets mostly highly-constrained environments with tight power budget; due to its simple structure and lack of complex combinational functions, the cipher has short critical paths (it can work at 1.9 Ghz in TSMC 90 nm technology when synthesized for best performance [22]) and is normally used in low-frequency systems (f O << f M /2). Also, Grain-80 has been the target of successful power analysis attacks [9], [15]- [17], which makes power analysis countermeasures necessary.…”

Section: B Transformation Of the Grain Ciphermentioning

confidence: 99%

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures

Mansouri

Dubrova

2013

2013 Euromicro Conference on Digital System Design

Self Cite

View full text Add to dashboard Cite

We introduce a power optimization technique for suppression countermeasures against Power Analysis attacks that can potentially be applied to any type of crypto-system implemented as a synchronous digital system. Since the power consumption of systems protected by suppression countermeasures is proportional to current peaks, we propose a simple transformation to move some of the switching activity of the crypto-system from the rising edge to the falling edge of the clock, so that current peaks are reduced. The transformation is easy to apply, requires only standard cell logic gates, has a low area overhead but can reduce the maximal working frequency of a system by at most a factor 2. We prove our method on an ASIC implementation of the Grain-80 stream cipher using SPICE-level simulation, obtaining 50% power savings compared to the non-optimized suppression countermeasure.

show abstract

Section: B Transformation Of the Grain Ciphermentioning

confidence: 99%

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures

Mansouri

Dubrova

2013

2013 Euromicro Conference on Digital System Design

Self Cite

View full text Add to dashboard Cite

show abstract

“…Our work can be used to complement the architectural approaches. For example, in [30] the FSR equivalence transformation [31] is applied to Grain-80 resulting in 50% delay improvement. The presented approach can be used on top of this transformation [31] to further reduce the area and power of Grain-80.…”

Section: Related Workmentioning

confidence: 99%

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Mansouri

Dubrova

2010

2010 IEEE International Conference on Computer Design

Self Cite

View full text Add to dashboard Cite

In this paper, we address the problem of lowoverhead implementation of Feedback Shift Registers (FSRs). We present a dynamic pulse latch which is based on transistors with two different channel lengths. The channel lengths are selected to make the latch suitable for replacing flip-flops in FSRs. The presented latch is 1.92 times smaller and 3.94 times less power consuming compared to the smallest standard flip-flop in the same technology. By re-implementing FSRs of Grain-80 stream cipher with the presented latch, we achieve 32.24% reduction in area, 36.77% reduction in total power, and 10.81% increase in the maximum clock frequency compared to the original, flipflop based version of Grain-80. If, in addition, the static time borrowing technique is applied, we achieve an additional 25.5% increase in the maximum clock frequency at the expense of 4.68% smaller gain in area and 2.67% smaller gain in total power. 978-1-4244-8935-0/10/$26.00 ©2010 IEEE

show abstract

“…The grain-128 supports the 128-bit key and an IV of 96 bits. This encryption is still very small and easy to be implemented in hardware [22]. In addition, the speed in hardware implementation can be easily increased.…”

Section: Random Number Generator (Rng)mentioning

confidence: 99%

“…The appropriate algorithm in our case is grain-128, because it supports the 128-bit key, and its initial vector is about 96 bits. This encryption is very small and easy to implement in hardware [22]. In addition, it is possible and easy to speed up the hardware design.…”

mentioning

confidence: 99%

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

et al. 2017

View full text Add to dashboard Cite

Abstract:The Elliptic Curve Digital Signature Algorithm (ECDSA) is the analog to the Digital Signature Algorithm (DSA). Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curves with the 163-bit key length recommended by the NIST (National Institute of Standards and Technology). It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip) and Random Number Generator IP (RNG IP). Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm 2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW). Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks.

show abstract

An Improved Hardware Implementation of the Grain Stream Cipher

Cited by 17 publications

References 8 publications

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures

Double-Edge Transformation for Optimized Power Analysis Suppression Countermeasures

Pulse latch based FSRs for low-overhead hardware implementation of cryptographic algorithms

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

Contact Info

Product

Resources

About