An implementation of the SANE Virtual Processor using POSIX threads

Tol, M.W. van; Jesshope, Chris; Lankamp, M.; Polstra, Simon

doi:10.1016/j.sysarc.2008.09.006

Cited by 22 publications

(23 citation statements)

References 4 publications

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“…A lot of studies have demonstrated that the parallelization architecture can greatly improve the image processing prototypes' efficiency [5,11,12,15,33]. POSIX Threads (Pthreads) is one of the most popular parallel programming technologies for the UNIX-like operation systems.…”

Section: Multi-threads Kmga Parallelizationmentioning

confidence: 99%

Design and evaluation of a parallel and optimized light–tissue interaction-based method for fast skin lesion assessment

Brost

Benezeth

et al. 2015

J Real-Time Image Proc

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In recent years, image processing technics have attracted much attention as powerful tools in the assessment of skin lesions from multispectral images. The Kubelka-Munk Genetic Algorithm (KMGA) is a novel method which has been developed for this diagnostic purpose. It combines the Kubelka-Munk light-tissue interaction model with the Genetic Algorithm optimization process, and allows quantitative measure of cutaneous tissue by computing skin parameter maps such as melanin concentration, volume blood fraction, oxygen saturation or epidermis/dermis thickness. However, its efficiency is seriously reduced by the mass floating-point operations for each pixel of the multispectral image, and this prevents the algorithm from reaching industrial standards related to cost, power and speed for clinical applications. In this paper, our work focuses on the improvement of this theoretical achievement. Therefore, we repropose a new C-based Parallel and Optimized KMGA (PO-KMGA) technique designed and optimized using multiple ways: KM model optimized re-writing, operation massively parallelized using POSIX threads, memory use optimization and routine pipelining with Intel C?? Compiler, etc.Intensive experiments demonstrate that our introduced PO-KMGA framework spends less than 10 min to finish a job that the conventional KMGA spends around two days to do in the same hardware environment with a similar algorithm performance.

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Section: Multi-threads Kmga Parallelizationmentioning

confidence: 99%

Design and evaluation of a parallel and optimized light–tissue interaction-based method for fast skin lesion assessment

Brost

Benezeth

et al. 2015

J Real-Time Image Proc

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“…The suggested concurrent programming model for this chip is based on forkjoin constructs where each created thread can define further concurrency hierarchically. This model is called SVP and is also applicable to current multicore architectures [21].…”

Section: Motivation and Backgroundmentioning

confidence: 99%

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

Uddin

Jesshope

Tol

et al. 2012

Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores Irfan-Ud-Din, M.; Jesshope, C.R.; van Tol, M.W.; Poss, R.C. General rightsIt is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulationsIf you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the material inaccessible and/or remove it from the website. Please Ask the Library: http://uba.uva.nl/en/contact, or a letter to: Library of the University of Amsterdam, Secretariat, Singel 425, 1012 WP Amsterdam, The Netherlands. You will be contacted as soon as possible. ABSTRACTThe current many-core architectures are generally evaluated by a detailed emulation with a cycle-accurate simulation of the execution time. However this detailed simulation of the architecture makes the evaluation of large programs very slow. Since the focus in many-core architecture is shifting from the performance of the individual core to the overall behavior of chip, high-level simulations are becoming necessary, which evaluate the same architecture at less detailed level and allow the designer to make quick and reasonably accurate design decisions. We have developed a high-level simulator for the design space exploration of the Microgrid, which is a many-core architecture comprised of many finegrained multi-threaded cores. This simulator allows us to investigate mapping and scheduling strategies of families (i.e. groups of threads) in developing an operating environment for the Microgrid. The previous method to evaluate the workload counted in basic blocks was inaccurate. The key problem is that with many concurrent threads the latency of certain instructions are hidden because of the multithreaded nature of the core. This paper presents a technique to manage the execution time of different types of instructions with thread concurrency. We believe to achieve high accuracy in evaluating programs in the high-level simulator.

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“…It is emphasised that many of these issues are relevant to the dynamic allocation of resources in other concurrent systems, where SVP is not implemented at the level of the ISA. For example, in [21], an implementation of SVP based on POSIX threads is described, which supports all of the actions described above. Notwithstanding this, the major thrust of this paper is directed towards many-core devices (microgrids).…”

Section: General Principlesmentioning

confidence: 99%

Operating Systems in Silicon and the Dynamic Management of Resources in Many-Core Chips

Jesshope

2008

Parallel Process. Lett.

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This discussion paper explores the problems of operating systems support when implementing concurrency controls at the level of the instruction set in processors designed for multi- and many-core chips. It introduces the SVP model and its implementation in DRISC processors to a level of detail required to understand these problems. The major contribution of the paper is in analysing the issues faced in porting operating system functionality onto such processors. The paper covers the issues of job scheduling, dynamic resource management, memory protection and security. It provides examples in μTC (a language based on the SVP model) of how resource management and security issues are managed. It concludes that the implementation of concurrency controls in a processors instruction set is very disruptive. However, the author sees no alternatives if mainstream computing is ever to be served effectively by multi- and many core processors.

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An implementation of the SANE Virtual Processor using POSIX threads

Cited by 22 publications

References 4 publications

Design and evaluation of a parallel and optimized light–tissue interaction-based method for fast skin lesion assessment

Design and evaluation of a parallel and optimized light–tissue interaction-based method for fast skin lesion assessment

Collecting signatures to model latency tolerance in high-level simulations of microthreaded cores

Operating Systems in Silicon and the Dynamic Management of Resources in Many-Core Chips

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