An Implementation of Handshake Join on FPGA

Oge, Yasin; Miyoshi, Takefumi; Kawashima, Hideyuki; Yoshinaga, Tsutomu

doi:10.1109/icnc.2011.22

Cited by 9 publications

(3 citation statements)

References 5 publications

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“…Teubner and Mueller (2011) presented handshake join that makes two input streams to flow by in opposing directions, which is highly amenable to parallelized execution. Oge et al (2011) showed an implementation of the handshake join on field-programmable gate arrays (FPGAs). Recently, Karnagel et al (2013) proposed an initial variant of a window join operator that is optimized for processors with heterogeneous execution units.…”

Section: Window Joinsmentioning

confidence: 99%

Time-slide window join over data streams

et al. 2014

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The join is an important operator in processing data streams. To produce outputs continuously over unbounded data streams, sliding windows are generally used to limit the scope of the join at a certain time. In the existing join algorithms, only a simple type of windows have been considered, which are updated whenever a new data item arrives on any input stream. On the other hand, a more common type of windows have not been addressed yet, whose intervals are updated periodically, i.e., slid by a predefined time interval. In this paper, we consider the time-slide windows in joining multiple data streams. The algorithm for the time-slide window join can vary according to (i) how frequently the join is evaluated and (ii) which structure is used for windowing. Regarding this, possible algorithms are discussed, and experimental results that compare their performances are provided in this paper.

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Section: Window Joinsmentioning

confidence: 99%

Time-slide window join over data streams

et al. 2014

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“…To the Copyright c 2012 The Institute of Electronics, Information and Communication Engineers best of our knowledge, this is the first paper that proposes a complete design of handshake join, implements it as a dedicated hardware on an FPGA device, and indicates buffer tuning for join and merge units. This paper is an extended version of the authors' previous work [5]. The present version shows further analysis regarding buffer-size optimization, and discusses static and adaptive buffer tuning for the proposed design.…”

Section: Introductionmentioning

confidence: 97%

Design and Implementation of a Handshake Join Architecture on FPGA

Oge

Miyoshi

Kawashima

et al. 2012

IEICE Trans. Inf. & Syst.

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SUMMARYA novel design is proposed to implement highly parallel stream join operators on a field-programmable gate array (FPGA), by examining handshake join algorithm for hardware implementation. The proposed design is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results indicate that the proposed implementation can handle considerably high input rates, especially at low match rates. Results of simulation conducted to optimize size of buffers included in join and merge units give a new intuition regarding static and adaptive buffer tuning in handshake join.

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“…For joining tables, hash joins are the most commonly used approach [19]. However, many examples of other types of table joins exist such as the merge join algorithm [3], the handshake join [16], etc.…”

Section: Related Workmentioning

confidence: 99%

Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique

Salami

Arcas-Abella

Sönmez

et al. 2017

Communications in Computer and Information Science

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Abstract. Extracting valuable information from the rapidly growing field of Big Data faces serious performance constraints, especially in the softwarebased database management systems (DBMS). In a query processing system, hash-based computational primitives such as the hash join and the group-by are the most time-consuming operations, as they frequently need to access the hash table on the high-latency off-chip memories and also to traverse whole the table. Subsequently, the hash collision is an inherent issue related to the hash tables, which can adversely degrade the overall performance. In order to alleviate this problem, in this paper, we present a novel pure hardware-based hash engine, implemented on the FPGA. In order to mitigate the high memory access latencies and also to faster resolve the hash collisions, we follow a novel design point. It is based on caching the hash table entries in the fast on-chip Block-RAMs of FPGA. Faster accesses to the correspondent hash table entries from the cache can lead to an improved overall performance. We evaluated the proposed approach by running hash-based table join and group-by operations of 5 TPC-H benchmark queries. The results show 2.9X -4.4X speedups over the cache-less FPGA-based baseline.

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An Implementation of Handshake Join on FPGA

Cited by 9 publications

References 5 publications

Time-slide window join over data streams

Time-slide window join over data streams

Design and Implementation of a Handshake Join Architecture on FPGA

Accelerating Hash-Based Query Processing Operations on FPGAs by a Hash Table Caching Technique

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