An imager with built-in image-velocity computation capability

Abstract

An imager with built-in image-velocity computation capability is described. The image-velocity computation technique is based on signals propagating on delay lines. Silicon implementation using ~F-C M O S technology is described. Experimental results show that a computational error of less than 20% can be achieved using currently available fabrication technology. This figure can be reduced by using larger arrays and better implementations of delay gates.

Real-time edge detection and image segmentation

“…Consequently, the sum of the inhibition currents, 11 .... , I N, supplied to the pixel located on the bright side of the image edge will also be low. According to equation (2), this leads to a higher Io for the pixels located on the bright side of the image edge (which encode the image edge). As a result, Fig.…”

“…A better method of edge detection is based on the equation Io = U Io = U 16 -{I1 + 12 + "" + IN} (2) Note that equation (2) is derived from equation (1) by multiplying equation (1) by N. Thus, the output current expressed by equation (2) is N times larger than that expressed by equation (1). A current-mirror-based circuit implementing equation (2) is shown in figure 2.…”

“…Here, the pixel containing photodiode A is chosen. For this case, the condition for the detection of an image edge is g>0 (4) where I o is given by equation (2). No image edge is present if…”

“…Moreover, the size of the edge detector must occupy a small area so that when other processing circuits (such as those performing image segmentation or image velocity computation [1], [2]) are integrated with it the resulting pixel density is not impractically low. This paper describes work leading to the implementation of a viable edge-detection and image segmentation system on silicon.…”