An H.264/AVC scalable extension and high profile HDTV 1080p encoder chip

Chen, Yi‐Hau; Chuang, T. J.; Chen, Yu-Jen; Li, Chung-Te; Hsu, Chia‐Jung; Chien, Shao-Yi; Chen, Liang-Gee

doi:10.1109/vlsic.2008.4585969

Cited by 39 publications

(12 citation statements)

References 4 publications

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“…An H.264 encoder for high profile, which "firstly" supported Scalable Video Coding (SVC), was proposed in [7]. Figure 3 illustrates its 2-stage frame pipelining architecture and its B-frame parallel scheme.…”

Section: Scalability Andmentioning

confidence: 99%

“…From all these modifications and improvements, the high profile-SVC encoder, even with computation four times more complex than a baseline profile encoder, achieves comparable power consumption, i.e. only 306 mW in high profile and 411 mW with SVC for HDTV1080p video [7]. This area cost of this design can be estimated quite large when compared with classical schemes.…”

Section: Scalability Andmentioning

confidence: 99%

“…Inter-prediction and intra-prediction in the same stage can be executed in parallel or separately, thanks to the system controller decision. In the separate mode of execution, to save the power consumption, one of the [6] Y.-H. Chen [7] K. Iwata [15] T.-C. Chen [8] Y.-H. Chen [9] S. Mochizuki [16] Y.-K. Lin [18] H.-C. Chang [17] H. Kim [20] Figure 6. VENGME H.264/AVC encoder architecture.…”

Section: Architecturementioning

confidence: 99%

“…Therefore, parallel processing solutions such as DSP-based, stream processor-based, multi-core systems or dedicated VLSI hardware architectures must be addressed to respond to this demand. In particular, designing Large-Scale Integration (LSI) like H.264 video encoding systems is a recent design trend in implementing multimedia systems aimed at high-throughput design for high-definition (HD) video [6][7][8] and low power design for portable video [9]. Indeed, the main issue is to lower power consumption for intended applications such as video transmission and play back on mobile terminals, to support real-time video encoding/decoding on batterypowered devices and, obviously, programmable processors or DSP-based implementations which cannot meet this requirement.…”

Section: Introductionmentioning

confidence: 99%

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An Overview of H.264 Hardware Encoder Architectures Including Low-Power Features

Nguyen

Bui²,

Dang³

et al. 2014

REV-JEC

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Abstract-H.264 is the most popular video coding standard with high potent coding performance. For its efficiency, the H.264 is expected to encode real-time and/or high-definition video. However, the H.264 standard also requires highly complex and long lasting computation. To overcome these difficulties, many efforts have been deployed to increase encoding speed. Besides, with the revolution of portable devices, multimedia chips for mobile environments are more and more developed. Thus, power-oriented design for H.264 video encoders is currently a tremendous challenge. This paper discusses these trends and presents an overview of the state of the art on power features for different H.264 hardware encoding architectures. We also propose the VENGME's design, a particular hardware architecture of H.264 encoder that enables applying low-power techniques and developing power-aware ability. This low power encoder is a four-stage architecture with memory access reduction, in which, each module has been optimized. The actual total power consumption, estimated at Register-TransferLevel (RTL), is only 19.1 mW.

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Section: Scalability Andmentioning

confidence: 99%

Section: Scalability Andmentioning

confidence: 99%

Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Overview of H.264 Hardware Encoder Architectures Including Low-Power Features

Nguyen

Bui²,

Dang³

et al. 2014

REV-JEC

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“…There are many previous works trying to bring up the hardware solution for FME in HDTV specifications [2][3][4] [5]. The contribution of these works can be roughly classified into two approaches.…”

Section: Problem Statementmentioning

confidence: 99%

Single-iteration full-search fractional motion estimation for quad full HD H.264/AVC encoding

Tsung

Chen

Ding

et al. 2009

2009 IEEE International Conference on Multimedia and Expo

Self Cite

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Fractional motion estimation (FME) is widely used in video compression standards. In H.264/AVC, the precision of motion vector is down to quarter pixels to improve the coding efficiency. However, FME occupies over 45% of the computation complexity in an H.264 encoder and this high complexity limits the processing capability. In this paper, a single-iteration full search FME is proposed. By the algorithm and architecture co-optimization, the bandwidth to the frame buffer is reduced by 31%. Furthermore, 82% of circuit area for the Hadamard transformation and subtraction are saved from the direct implementation. Compared with prior arts, the proposed design supports 3.39 × higher throughput with only 0.02 dB PSNR drop. Thus, the specification of 4096 × 2160 quad full high definition H.264/AVC FME processing can be achieved.

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