An FPGA-specific approach to floating-point accumulation and sum-of-products

Abstract-Recent increase in the complexity of the circuits has brought high-level synthesis tools as a must in the digital circuit design. However, these tools come with several limitations, and one of them is the efficient use of pipelined arithmetic operators. This paper explains how to generate efficient hardware with pipelined operators for regular codes with perfect loop nests. The part to be mapped to the operator is identified, then the program is scheduled so that each operator result is available exactly at the time it is needed by the operator, keeping the operator busy and avoiding the use of a temporary buffer. Finally, we show how to generate the VHDL code for the control unit and how to link it with specialized pipelined floating-point operators generated using open-source FloPoCo tool. The method has been implemented in the Bee research compiler and experimental results on DSP kernels show promising results with a minimum of 94% efficient utilization of the pipelined operators for a complex kernel.

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“…• specialized operators such as: squarers, faithful multipliers 1 , FPGA-specific FP accumulators [18].…”

Section: Flopoco -A Tool For Generating Computational Kernelsmentioning

confidence: 99%

Automatic Generation of FPGA-Specific Pipelined Accelerators

Alias

Pasca

Plesco

2011

Lecture Notes in Computer Science

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“…Dinechin et al studies two common situations where the flexibility of FPGAs allows one to design application specific floating-point operators [12]. It address the problem for applications involving the addition and sum-of-product of a large number of floating-point values.…”

Section: Related Workmentioning

confidence: 99%

Reconfigurable Out-of-Order System for Fluid Dynamics Computation Using Unstructured Mesh

Akamine

Talip

Osana

et al. 2014

IEICE Trans. Inf. & Syst.

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SUMMARYComputational fluid dynamics (CFD) is an important tool for designing aircraft components. FaSTAR (Fast Aerodynamics Routines) is one of the most recent CFD packages and has various subroutines. However, its irregular and complicated data structure makes it difficult to execute FaSTAR on parallel machines due to memory access problem. The use of a reconfigurable platform based on field programmable gate arrays (FPGAs) is a promising approach to accelerating memory-bottlenecked applications like FaSTAR. However, even with hardware execution, a large number of pipeline stalls can occur due to read-after-write (RAW) data hazards. Moreover, it is difficult to predict when such stalls will occur because of the unstructured mesh used in FaSTAR. To eliminate this problem, we developed an out-of-order mechanism for permuting the data order so as to prevent RAW hazards. It uses an execution monitor and a wait buffer. The former identifies the state of the computation units, and the latter temporarily stores data to be processed in the computation units. This out-of-order mechanism can be applied to various types of computations with data dependency by changing the number of execution monitors and wait buffers in accordance with the equations used in the target computation. An out-of-order system can be reconfigured by automatic changing of the parameters. Application of the proposed mechanism to five subroutines in FaSTAR showed that its use reduces the number of stalls to less than 1% compared to without the mechanism. In-order execution was speeded up 2.6-fold and software execution was speeded up 2.9-fold using an Intel Core 2 Duo processor with a reasonable amount of overhead. key words: computational fluid dynamics (CFD), field programmable gate array (FPGA), scientific computations, reconfigurable hardware, out-oforder system

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“…One benefit of the singleaccumulator is that it can quickly be converted back into a floating-point number for consumption on chip, but this is not important for Monte-Carlo applications. 2 …”

Section: Related Workmentioning

confidence: 99%

“…The most directly comparable method has been developed within the FloPoCo project [2], where the same idea of using a large fixed-point accumulator is used to provide increased accuracy without sacrificing speed. However, their approach is to choose a fixedrange for the floating-point accumulator, then to shift each floating-point mantissa to the correct position before adding to the accumulator.…”

Section: Related Workmentioning

confidence: 99%