An FPGA platform for on-line topology exploration of spiking neural networks

Upegui, Andrés; Peña-Reyes, Carlos Andrés; Sánchez, Eduardo García

doi:10.1016/j.micpro.2004.08.012

Cited by 84 publications

(47 citation statements)

References 14 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Instantiation of LUTs in VHDL and then automatic place and route is more convenient, flexible, and requires less expert knowledge than earlier EHW approaches, describing manually placed components with e.g. the FPGA Editor [2]. For more complex EHW architectures, several LUTs may have to be combined in order to achieve the desired functionality, and the complexity may prove to be a design challenge.…”

Section: Discussionmentioning

confidence: 99%

“…Combinations of these component states can then be instantiated using partial reconfiguration. The drawback of this approach is that the configuration granularity is relatively coarse, and is thus in the context of EHW mostly suitable for modifying architecture parameters [2], [3] or for evolution of systems using high level functions of a certain complexity [4], [5].…”

Section: Introductionmentioning

confidence: 99%

“…As the description of the bitstream format is not publicly accessible, reverse engineering has been employed to identify the locations of the lookup table (LUT) configuration bits, whereas the reverse engineering of the routing has been judged too complex and impractical [2]. Therefore, some reconfigurable EHW architectures with a fixed topology and variable LUT functions have been proposed, using Virtex [6], Virtex-II [7], [8], and more recently, Virtex-4 [9] devices.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Lookup table partial reconfiguration for an evolvable hardware classifier system

Glette

Kaufmann

2014

2014 IEEE Congress on Evolutionary Computation (CEC)

View full text Add to dashboard Cite

Abstract-The evolvable hardware (EHW) paradigm relies on continuous run-time reconfiguration of hardware. When applied on modern FPGAs, the technically challenging reconfiguration process becomes an issue and can be approached at multiple levels. In related work, virtual reconfigurable circuits (VRC), partial reconfiguration, and lookup table (LUT) reconfiguration approaches have been investigated. In this paper, we show how fine-grained partial reconfiguration of 6-input LUTs of modern Xilinx FPGAs can lead to significantly more efficient resource utilization in an EHW application. Neither manual placement nor any proprietary bitstream manipulation is required in the simplest form of the employed method. We specify the goal architecture in VHDL and read out the locations of the automatically placed LUTs for use in an online reconfiguration setting. This allows for an easy and flexible architecture specification, as well as possible implementation improvements over a hand-placed design. For demonstration, we rely on a hardware signal classifier application. Our results show that the proposed approach can fit a classification circuit 4 times larger than an equivalent VRC-based approach, and 6 times larger than a shift registerbased approach, in a Xilinx Virtex-5 device. To verify the reconfiguration process, a MicroBlaze-based embedded system is implemented, and reconfiguration is carried out via the Xilinx Internal Configuration Access Port (ICAP) and driver software.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Lookup table partial reconfiguration for an evolvable hardware classifier system

Glette

Kaufmann

2014

2014 IEEE Congress on Evolutionary Computation (CEC)

View full text Add to dashboard Cite

show abstract

“…Several chapters in [99] are dedicated to this subject, and more recent work can be found for instance in [170,53,77,33,125,116,150].…”

Section: Implementing Snnsmentioning

confidence: 99%

Computing with Spiking Neuron Networks

Paugam-Moisy

Bohté

2012

Handbook of Natural Computing

202

114

View full text Add to dashboard Cite

Spiking Neuron Networks (SNNs) are often referred to as the 3 rd generation of neural networks. Highly inspired from natural computing in the brain and recent advances in neurosciences, they derive their strength and interest from an accurate modeling of synaptic interactions between neurons, taking into account the time of spike firing. SNNs overcome the computational power of neural networks made of threshold or sigmoidal units. Based on dynamic event-driven processing, they open up new horizons for developing models with an exponential capacity of memorizing and a strong ability to fast adaptation. Today, the main challenge is to discover efficient learning rules that might take advantage of the specific features of SNNs while keeping the nice properties (general-purpose, easy-to-use, available simulators, etc.) of traditional connectionist models. This chapter relates the history of the "spiking neuron" in Section 1 and summarizes the most currently-in-use models of neurons and synaptic plasticity in Section 2. The computational power of SNNs is addressed in Section 3 and the problem of learning in networks of spiking neurons is tackled in Section 4, with insights into the tracks currently explored for solving it. Finally, Section 5 discusses application domains, implementation issues and proposes several simulation frameworks.

show abstract

“…In reconfigurable architectures, the model can modify the hardware configuration of the chip while the simulation is running. Either through component swapping [12] or network remapping [56], these approaches seek to circumvent scalability limitations, with some success, but with both FPGA's and GPU's scalability has proven to be the main problem, with FPGA's running into routing barriers due to their circuit-switched fabric [33] and GPU's running into memory access barriers. Even more problematic has been power consumption: a typical large FPGA may dissipate ∼ 50W and a GPU accelerator ∼ 200W.…”

Section: Adapted General-purpose Hardwarementioning

confidence: 99%

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Rast

Navaridas

Jin

et al. 2011

Int J Parallel Prog

View full text Add to dashboard Cite

Neural networks present a fundamentally different model of computation from the conventional sequential digital model, for which conventional hardware is typically poorly matched. However, a combination of model and scalability limitations has meant that neither dedicated neural chips nor FPGA's have offered an entirely satisfactory solution. SpiNNaker introduces a different approach, the "neuromimetic" architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. This parallel multiprocessor employs an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. Nonetheless, event handling, particularly packet servicing, requires careful and innovative design in order to avoid local processor congestion and possible deadlock. We explore the impact that spatial locality, temporal causality and burstiness of traffic have on network performance, using tunable, biologically similar synthetic traffic patterns. Having established the viability of the system for real-time operation, we use two exemplar neural models to illustrate how to implement efficient event-handling service routines that mitigate the problem of burstiness in the traffic. Extending work published in ACM Computing Frontiers 2010 with on-chip testing, simulation results indicate the viability of SpiNNaker for large-scale neural modelling, while emphasizing the need for effective burst management and network mapping. Ultimately, the goal is the creation of a library-based development system that can translate a high-level neural model from any description 123Int J Parallel Prog environment into an efficient SpiNNaker instantiation. The complete system represents a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale.

show abstract

An FPGA platform for on-line topology exploration of spiking neural networks

Cited by 84 publications

References 14 publications

Lookup table partial reconfiguration for an evolvable hardware classifier system

Lookup table partial reconfiguration for an evolvable hardware classifier system

Computing with Spiking Neuron Networks

Managing Burstiness and Scalability in Event-Driven Models on the SpiNNaker Neuromimetic System

Contact Info

Product

Resources

About