An FPGA memcached appliance

Chalamalasetti, Sai Rahul; Lim, Kevin; Wright, Mitch; AuYoung, Alvin; Ranganathan, Parthasarathy; Margala, Martin

doi:10.1145/2435264.2435306

Cited by 73 publications

(36 citation statements)

References 6 publications

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“…Given an input key, a hash accelerator computes the value using a hash algorithm described in [11]. The value is then used to index four SRAMs whose content is compared against the input key to determine a hit.…”

Section: Single Acceleratorsmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

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Hardware specialization, in the form of accelerators that provide custom datapath and control for specific algorithms and applications, promises impressive performance and energy advantages compared to traditional architectures. Current research in accelerator analysis relies on RTL-based synthesis flows to produce accurate timing, power, and area estimates. Such techniques not only require significant effort and expertise but are also slow and tedious to use, making large design space exploration infeasible. To overcome this problem, we present Aladdin, a pre-RTL, power-performance accelerator modeling framework and demonstrate its application to system-on-chip (SoC) simulation. Aladdin estimates performance, power, and area of accelerators within 0.9%, 4.9%, and 6.6% with respect to RTL implementations. Integrated with architecture-level core and memory hierarchy simulators, Aladdin provides researchers an approach to model the power and performance of accelerators in an SoC environment.

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Section: Single Acceleratorsmentioning

confidence: 99%

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Shao¹,

Reagen²,

Wei³

et al. 2014

2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA)

118

117

View full text Add to dashboard Cite

show abstract

“…Chalamalasetti et al's work was the first to try to utilize FPGA for accelerating memcached [5]. The system mainly consists of two parts: a network processing part and a memcached application part.…”

Section: Related Workmentioning

confidence: 99%

“…In view of such extensive use, improving the memcached performance would have a large impact on web services' response. In fact, researchers have investigated the suitability of various hardware platforms for running memcached, from multiple low power CPUs [11], [12], [13] to many-core processors [3] and FPGAs [5]. Meanwhile, FPGA-based memcached systems are outperforming high performance CPUs such as Intel ® Xeon ® by an order of magnitude [4].…”

Section: Introductionmentioning

confidence: 99%

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface

Fukuda

Inoue²,

Takenaka³

et al. 2015

Journal of Information Processing

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Abstract:Memcached has been widely accepted as a technology to improve the response speed of web servers by caching data on DRAMs in distributed servers. Because of its importance, the acceleration of memcached has been studied on various platforms. Among them, FPGA looks the most attractive platform to run memcached, and several research groups have tried to obtain a much higher performance than that of CPU out of it. The difficulty encountered there, however, is how to manage large-sized memory (gigabytes of DRAMs) from memcached hardware built in an FPGA. Some groups are trying to solve this problem by using an embedded CPU for memory allocation and another group is employing an SSD. Unlike other approaches that try to replace memcached itself on FPGAs, our approach augments the software memcached running on the host CPU by caching its data and some operations at the FPGAequipped network interface card (NIC) mounted on the server. The locality of memcached data enables the FPGA NIC to have a fairly high hit rate with a smaller memory. In this paper, we describe the architecture of the proposed NIC cache, and evaluate the effectiveness with a standard key-value store (KVS) benchmarking tool. Our evaluation shows that our system is effective if the workload has temporal locality but does not handle workloads well without such a characteristic. We further propose methods to overcome this problem and evaluate them. As a result, we estimate that the latency improved by up to 3.5 times over software memcached running on a high performance CPU.

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“…FPGA accelerators are currently being used in database management systems [4], in providing web services [15], as well as in other domains such as machine learning [23] and bioinformatics [27].…”

Section: Related Workmentioning

confidence: 99%

Scalable multi-access flash store for big data analytics

Jun

Liu

Fleming

et al. 2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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For many "Big Data" applications, the limiting factor in performance is often the transportation of large amount of data from hard disks to where it can be processed, i.e. DRAM. In this paper we examine an architecture for a scalable distributed flash store which aims to overcome this limitation in two ways. First, the architecture provides a highperformance, high-capacity, scalable random-access storage. It achieves high-throughput by sharing large numbers of flash chips across a low-latency, chip-to-chip backplane network managed by the flash controllers. The additional latency for remote data access via this network is negligible as compared to flash access time. Second, it permits some computation near the data via a FPGA-based programmable flash controller. The controller is located in the datapath between the storage and the host, and provides hardware acceleration for applications without any additional latency. We have constructed a small-scale prototype whose network bandwidth scales directly with the number of nodes, and where average latency for user software to access flash store is less than 70µs, including 3.5µs of network overhead.

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An FPGA memcached appliance

Cited by 73 publications

References 6 publications

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures

Enhancing Memcached by Caching Its Data and Functionalities at Network Interface

Scalable multi-access flash store for big data analytics

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