An FPGA implementation of HW/SW codesign architecture for H.263 video coding

Atitallah, Ahmed Ben; Kadionik, Patrice; Ghozzi, Fahmi; Nouel, Patrice; Nouri, Mohammad; Lévi, H.

doi:10.1016/j.aeue.2006.11.001

Cited by 20 publications

(9 citation statements)

References 37 publications

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“…The software part, concerning reading/writing pixels and restoring filtered image, can be running on Nios-II softcore processor embedded in FPGA. The main processing core of our system is the Nios-I1 CPU which is connected to hardware peripherals via a custom ALTERA Avalon bus [10]. The implemented design is shown in FigA.…”

Section: Experiments Al Validation Resultsmentioning

confidence: 99%

Hardware implementation and experiment validation of the VDDRHF color image filter

Boudabous¹,

Atitallah²,

Khriji

et al. 2010

2010 7th International Multi- Conference on Systems, Signals and Devices

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This paper proposes a novel FPGA implementation of Vector Directional Distance Rational Hybrid Filter) (VDDRHF) for mixed noise suppression and fme-details preservation in color images. The Implementation was done, based on FPGA HW/SW validation using efficient hardware optImIzations and non linear function approximations. The validation using FPGA board confirms the color image quality preservation. Our proposed architecture proves that HW/SW co-design present a high timing performance compared to software based solutions.Ind e x T e rms-VDDRHF filter, color image, architecture, FPGA implementation, Nios-II, validation.

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Section: Experiments Al Validation Resultsmentioning

confidence: 99%

Hardware implementation and experiment validation of the VDDRHF color image filter

Boudabous¹,

Atitallah²,

Khriji

et al. 2010

2010 7th International Multi- Conference on Systems, Signals and Devices

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“…The tested code was then compiled for the Nios II Integrated Device Electronics (IDE) and deployed in the development board. The standard HW/SW co-design process can consist of three main steps [10], which include the implementation of the Algorithm into software, followed by an analysis of the program with profiling to detect the critical parts of Algorithm, then efficiently implement the algorithm in hardware. The detection of critical part of the software and the optimization will be discussed in the next section.…”

Section: Hw/sw Co-design Encoding Systemmentioning

confidence: 99%

Towards a Mobile Implementation of Waaves for Certified Medical Image Compression in E-Health Applications

Mhedhbi

Hachicha

Garda

et al. 2013

Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering

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Abstract. In this article, we present two studies that pave the way towards a mobile implementation of the WAAVES certified medical image compression encoder. On the algorithmic side, we compared three techniques to increase the compression rate. The obtained results show a significant bit-rate reduction, around 40% with respect to the WAAVES encoder, while keeping the same visual quality. On the architectural side, we describe the HW/SW co-design of an architecture implemented in a FPGA platform. By using code profiling, critical portions of the code were identified, then two methods for hardware acceleration were used to implement the critical part of the coder. The tests were done on a StratixIVGX230 FPGA and the results showed that HW/SW co-design could achieve up to 20x performance gain in the critical portion. The combination of these results demonstrates the feasibility of a mobile implementation of the WAAVES certified medical image coder suitable for e-health applications.

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“…A file system is available for data storage. A network connectivity based on Ethernet protocols is well suited for data recovering [16].…”

Section: Hardware-software Filter Designmentioning

confidence: 99%

Reconfigurable architecture of VDF filter for multidimensional data

Atitallah

Boudabous

Khriji

et al. 2012

Circuit Theory & Apps

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International audienceIn this paper, we present a hardware reconfigurable architecture of vector directional filter (VDF) and an experimental validation based on HW/SW implementation context. An FPGA with a Nios II processor combines the benefits of a programmable logic component as well as a microprocessor. VDF is very useful in multidimensional data (such as color images) for noise removal and details preservation. Comparative results between simulations of ANSI-C and hardware implementation are given. An estimate method of nonlinear function is presented and serves as an approximation for the appropriate hardware implementation on FPGA. Finally, to verify the functionality of the implementation, a validation state using FPGA platform has been performed. This validation demonstrated that our implementation hardware system speeds up the filtering process as well as preserving a high data quality (image quality

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An FPGA implementation of HW/SW codesign architecture for H.263 video coding

Cited by 20 publications

References 37 publications

Hardware implementation and experiment validation of the VDDRHF color image filter

Hardware implementation and experiment validation of the VDDRHF color image filter

Towards a Mobile Implementation of Waaves for Certified Medical Image Compression in E-Health Applications

Reconfigurable architecture of VDF filter for multidimensional data

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