An FPGA implementation of a flexible architecture for H.263 video coding

Garrido, M.J.; Sanz, C.; Jimenez, M.; Menesses, J.M.

doi:10.1109/tce.2003.1196439

Cited by 9 publications

(2 citation statements)

References 12 publications

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“…In this context, it is useful to consider the design of a dedicated processor to perform the function of the MTS core as part of a VVC full implementation. Thus, such a full implementation could be composed of a multicore general purpose processor (GPP) and one or more dedicated processors that execute parts of the algorithm and act as accelerators [6].…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

et al. 2020

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Versatile video coding (VVC) will be released by 2020, and it is expected to be the nextgeneration video coding standard. One of its enhancements is multiple transform selection (MTS) for core transform. MTS uses three different types of 2D discrete sine/cosine transforms (DCT-II, DCT-VIII and DST-VII) and up to 64 × 64 transform unit sizes. With this schema, significant enhancements of the compression ratio are obtained at the expense of more computational complexity on both encoders and decoders. In this paper, a deeply pipelined high-performance architecture is proposed that implements the three transforms for sizes from 4 × 4 to 64 × 64 according to working draft 4 of the standard. The design has been described in very high-speed integrated circuit hardware description language (VHDL), and it has been prototyped in a system on a programmable chip (SoPC). It is able to process up to 64 fps@3840 × 2.160 for 4 × 4 transform sizes. To the best of our knowledge, this is the first implementation of an architecture for VVC MTS supporting the 64 × 64 size. INDEX TERMS FPGA, hardware architecture, multiple transform selection, pipeline, SoPC, versatile video coding. * The architecture proposed in this paper has been implemented and tested in accordance with WD 4. † The number of multiplications required by a direct implementation of a 2D N×N point DCT/DST is N 2 .

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Section: Introductionmentioning

confidence: 99%

An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core

et al. 2020

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“…Field programmable gate arrays (FPGAs) have a strong point in design flexibility, adaptability and design cycle. Nowadays, a fully digital implementation of signal processing applications is the desired choice because high performance can be achieved at reasonable cost and quick design on FPGAs [4]- [5]. Although bio-mimetic digital implementation is very little work to be done, at least we can find out Summerfield and Lyon [6] implemented a cochlear model of a bit-serial technology based on a serial cascade of non-linear second order lowpass filters on ASIC.…”

Section: Introductionmentioning

confidence: 99%

Bat on an FPGA: a biomimetic implementation of a highly parallel signal processing system

Clarke

Lin

Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004.

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The advent of multi-million gate FPGAs with hardware support for multiplication gives rise to the opportunity to recreate a significant portion of the front end of a Bat cochlear using this technology. In this paper we describe the implementation of this bio-mimetic cochlear and show that the whilst the performance required for a real-time implementation is significantly in excess of that possible from a digital signal processor, it is entirely suited to single device FPGA implementation.

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