An FPGA co-processor implementation of Homomorphic Encryption

Cousins, David Bruce; Golusky, J.; Rohloff, Kurt; Sumorok, Daniel

doi:10.1109/hpec.2014.7040950

Cited by 23 publications

(12 citation statements)

References 6 publications

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“…FPGAs and GPUs may be considered more flexible and cheaper compared to ASICs making them more popular as hardware accelerators. To the best of our knowledge, the first work that employed FPGAs for HE is due to Cousins et al [CGRS14]. Their work introduces elementary building blocks for implementing an NTRU-based FHE [SS11] using FPGA and Matlab Simulink.…”

Section: Literature Reviewmentioning

confidence: 99%

High-Performance FV Somewhat Homomorphic Encryption on GPUs: An Implementation using CUDA

Badawi

Veeravalli

Mun

et al. 2018

TCHES

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Homomorphic encryption (HE) offers great capabilities that can solve a wide range of privacy-preserving computing problems. This tool allows anyone to process encrypted data producing encrypted results that only the decryption key’s owner can decrypt. Although HE has been realized in several public implementations, its performance is quite demanding. The reason for this is attributed to the huge amount of computation required by secure HE schemes. In this work, we present a CUDAbased implementation of the Fan and Vercauteren (FV) Somewhat HomomorphicEncryption (SHE) scheme. We demonstrate several algebraic tools such as the Chinese Remainder Theorem (CRT), Residual Number System (RNS) and Discrete Galois Transform (DGT) to accelerate and facilitate FV computation on GPUs. We also show how the entire FV computation can be done on GPU without multi-precision arithmetic. We compare our GPU implementation with two mature state-of-the-art implementations: 1) Microsoft SEAL v2.3.0-4 and 2) NFLlib-FV. Our implementation outperforms them and achieves on average 5.37x, 7.37x, 22.22x, 5.11x and 13.18x (resp. 2.03x, 2.94x, 27.86x, 8.53x and 18.69x) for key generation, encryption, decryption, homomorphic addition and homomorphic multiplication against SEAL-FVRNS (resp. NFLlib-FV).

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Section: Literature Reviewmentioning

confidence: 99%

High-Performance FV Somewhat Homomorphic Encryption on GPUs: An Implementation using CUDA

Badawi

Veeravalli

Mun

et al. 2018

TCHES

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“…Acceleration of YASHE and LTV Schemes. Several works [19,20,23,27,49,50] focus on improving the performance of YASHE [10] and LTV [45] schemes or their variants. These constructions -based on an overstretched NTRU assumption -are subject to a subfield lattice attack [3] and are no longer secure.…”

Section: Large-integer Multiplication Hardware Accelerationmentioning

confidence: 99%

“…Prior work that propose customized hardware for non-CKKS schemes have taken one of these approaches: (i) Designing co-processors that only accelerate certain low-level ring operations [14,19,20,30,39,61]; high-level operations are performed on the CPU-side, which makes the coprocessors of limited practical use. (ii) Storing intermediate results on off-chip memory, which significantly degrades the performance [51] to the extent that it can be worse than naive software execution [53].…”

Section: Introductionmentioning

confidence: 99%

Heax

Riazi

Laine

Pelton

et al. 2020

Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Syste

142

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With the rapid increase in cloud computing, concerns surrounding data privacy, security, and confidentiality also have been increased significantly. Not only cloud providers are susceptible to internal and external hacks, but also in some scenarios, data owners cannot outsource the computation due to privacy laws such as GDPR, HIPAA, or CCPA. Fully Homomorphic Encryption (FHE) is a groundbreaking invention in cryptography that, unlike traditional cryptosystems, enables computation on encrypted data without ever decrypting it. However, the most critical obstacle in deploying FHE at large-scale is the enormous computation overhead. In this paper, we present HEAX, a novel hardware architecture for FHE that achieves unprecedented performance improvements. HEAX leverages multiple levels of parallelism, ranging from ciphertext-level to fine-grained modular arithmetic level. Our first contribution is a new highlyparallelizable architecture for number-theoretic transform (NTT) which can be of independent interest as NTT is frequently used in many lattice-based cryptography systems. Building on top of NTT engine, we design a novel architecture for computation on homomorphically encrypted data. Our implementation on reconfigurable hardware demonstrates 164-268× performance improvement for a wide range of FHE parameters.

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“…While prior work has proposed several FHE accelerators, they do not meet this goal. Prior FHE accelerators [20,21,27,65,66,71] target individual FHE operations, and miss important ones that they leave to software. These designs are FPGA-based, so they are small and miss the data movement issues facing an FHE ASIC accelerator.…”

Section: Introductionmentioning

confidence: 99%

F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version)

Feldmann,

Samardzic,

Krastev

et al. 2021

Preprint

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Fully Homomorphic Encryption (FHE) allows computing on encrypted data, enabling secure offloading of computation to untrusted servers. Though it provides ideal security, FHE is expensive when executed in software, 4 to 5 orders of magnitude slower than computing on unencrypted data. These overheads are a major barrier to FHE's widespread adoption.We present F1, the first FHE accelerator that is programmable, i.e., capable of executing full FHE programs. F1 builds on an indepth architectural analysis of the characteristics of FHE computations that reveals acceleration opportunities. F1 is a wide-vector processor with novel functional units deeply specialized to FHE primitives, such as modular arithmetic, number-theoretic transforms, and structured permutations. This organization provides so much compute throughput that data movement becomes the key bottleneck. Thus, F1 is primarily designed to minimize data movement. Hardware provides an explicitly managed memory hierarchy and mechanisms to decouple data movement from execution. A novel compiler leverages these mechanisms to maximize reuse and schedule off-chip and on-chip data movement.We evaluate F1 using cycle-accurate simulation and RTL synthesis. F1 is the first system to accelerate complete FHE programs, and outperforms state-of-the-art software implementations by gmean 5,400× and by up to 17,000×. These speedups counter most of FHE's overheads and enable new applications, like real-time private deep learning in the cloud.

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An FPGA co-processor implementation of Homomorphic Encryption

Cited by 23 publications

References 6 publications

High-Performance FV Somewhat Homomorphic Encryption on GPUs: An Implementation using CUDA

High-Performance FV Somewhat Homomorphic Encryption on GPUs: An Implementation using CUDA

Heax

F1: A Fast and Programmable Accelerator for Fully Homomorphic Encryption (Extended Version)

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